Semiconductor memory

• US 5,956,287 A
• Filed: 10/29/1997
• Issued: 09/21/1999
• Est. Priority Date: 11/01/1996
• Status: Expired due to Fees

• Current Assignee: Oki Semiconductor Company Limited (ROHM Co., Ltd.)
• Original Assignee: OKI Electric Industry Company Limited
• Inventors: Morikawa, Kouichi
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): NGUYEN, HIEN N
• Application Number:
  US08/959,857
• Time in Patent Office: 692 Days
• Field of Search: 365/230.05, 365/230.08, 365/189.05
• US Class Current: 365/230.05
• CPC Class Codes: G06F 5/10 having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory G06F5/065 takes precedence

Abstract

The present invention provides a semiconductor memory capable of improving a write address generator which performs complained control by using many gates and capable of reducing layout area. A FIFO semiconductor memory having plural input ports is provided with a memory array MARRAY of m-word×n bit×2-having 1W1R cell, a write address generator WAG consisted of a shift register, a valid bit VB of m-word×2-bit having 1W1R cell, a write buffer WDBV for the valid bit, a valid bit sense amplifier SAV, a read control RCTL judging validness of read data and a read address generator having a circuit controlling update of read address.

Claims

1. A semiconductor memory comprising:

a memory cell array;

a write address generator generating sequential addresses to be written in the memory cell array;

a validity register;

a write buffer writing a validity bit into the validity register;

a read address generator generating a read address for the memory cell array; and

a read controller judging validity of read data from the memory cell array in accordance with the validity bit read from the validity register.

2. A semiconductor memory according to the claim 1, wherein said semiconductor memory is a FIFO (First-In First-Out) semiconductor memory having plural input ports,

wherein said memory cell array is m-word×

n-bit×

2 with a 1W1R cell,

wherein said validity register is m-word×

2-bit, and

wherein said write address generator includes a shift register.

3. A semiconductor memory according to the claim 2, further comprising:

a first column selector for selecting first channels from a first m-word×

n-bit portion of the memory cell array;

a second column selector for selecting second channels from a second m-word×

n-bit portion of the memory cell array; and

a sense amplifier connected to the first and second column selectors for reading selected channel data by time-sharing.

4. A semiconductor memory according to the claim 3, wherein, further comprising:

a first local word driver provided for the first portion of the memory cell arrays; and

a second local word driver provided for the second portion of the memory cell array,

wherein the first and second local word drivers each receive a channel selection signal from said read controller.

5. A FIFO (First-In First-Out) semiconductor memory, comprising:

a memory cell array;

a write address generator generating sequential addresses to be written in the memory cell array;

a validity register with a 1W1R cell;

a write buffer for writing a validity bit into the validity register;

a read controller judging the validity of read data from the memory cell array; and

a read address generator, including a circuit for controlling updating of a read address for the memory cell.

6. The FIFO semiconductor memory of claim 5, wherein said memory cell array is m-word×

n-bit×

2 with a 1W1R cell, and wherein said validity register is m-word×

2-bit.

7. The FIFO semiconductor memory of claim 6, further comprising:

a first sense amplifier for reading first column data from a first m-word×

n-bit portion of the memory cell array;

a second sense amplifier for reading second column data from a second m-word×

n-bit portion of the memory cell array; and

a selector connected to the first and second sense amplifiers for selecting read data corresponding to said validity judgment of said read controller according to a validity bit read from said validity register.

8. The FIFO semiconductor memory of claim 6, further comprising:

a first column selector for selecting first channels from a first m-word×

n-bit portion of the memory cell array;

a second column selector for selecting second channels from a second m-word×

n-bit portion of the memory cell array; and

a sense amplifier connected to the first and second column selectors for reading selected channel data by time-sharing.

9. The FIFO semiconductor memory of claim 8, further comprising:

a first local word driver provided for the first portion of the memory cell array; and

a second local word driver provided for the second portion of the memory cell array,

wherein the first and second local word drivers each receive a channel selection signal from said read controller.

10. The FIFO semiconductor memory of claim 6, wherein the FIFO has plural input ports and further comprises:

a first data signal multiplexer receiving a first plurality of data signals from said plural input ports and generating therefrom a first multiplexed data signal;

a second data signal multiplexer receiving a second plurality of data signals from said plural input ports and generating therefrom a second multiplexed data signal;

a first write request signal multiplexer receiving a first plurality of write request signals from said plural input ports and generating therefrom a first multiplexed write request signal, and providing said first multiplexed write request signal to said write address generator and to said write buffer;

a second write request signal multiplexer receiving a second plurality of write request signals from said plural input ports and generating therefrom a second multiplexed write request signal, and providing said second multiplexed write request signal to said write address generator and to said write buffer;

a second write buffer receiving said first multiplexed data signal; and

a third write buffer receiving said second multiplexed data signal,

said second and third write buffers producing write data for said memory cell array.