Performance monitoring and test system for a telephone network

• US 5,956,324 A
• Filed: 10/30/1997
• Issued: 09/21/1999
• Est. Priority Date: 04/02/1992
• Status: Expired due to Term

• Current Assignee: Morgan Guaranty Trust Company of New York As Administrative Agent
• Original Assignee: Applied Digital Access, Inc. (Lumentum Holdings Inc.)
• Inventors: Engdahl, Thomas L., Hartmann, Paul R., Cadieux, Kevin, Pope, Kevin
• Primary Examiner(s): Olms, Douglas W.
• Assistant Examiner(s): VINCENT, DAVID ROBERT
• Application Number:
  US08/960,775
• Time in Patent Office: 691 Days
• Field of Search: 370/242, 370/248, 370/362, 370/250, 370/241, 370/244, 370/252, 370/522, 370/535, 371/20.1, 379/9, 379/1, 379/10, 379/14, 379/15
• US Class Current: 370/242
• CPC Class Codes: H04J 3/0608 Detectors therefor, e.g. correlators, state machines
• CPC Class Codes: H04J 3/0623 Synchronous multiplexing systems, e.g. synchronous digital hierarchy/synchronous optical network (SDH/SONET), synchronisation with a pointer process
• CPC Class Codes: H04J 3/14 Monitoring arrangements for SDH/SONET rings H04J3/085
• CPC Class Codes: H04M 3/22 Arrangements for supervision, monitoring or testing
• CPC Class Codes: H04M 3/244 for multiplex systems

Abstract

A DS3 level access, monitor and test system for a telephone network. The system provides selective, and hitless, bit overwrite in any of the embedded DS1, DS0 and subrate channels in a DS3 signal. Multiple DS0 and subrate channels can be tested via the asynchronous time slot interchange in conjunction with the recombiner of the present invention. The present invention further includes a lookahead reframer for framing to the DS3 signal. The present invention also includes a facilities data link (FDL) handler for capturing the FDL channel data in every DS1 channel in a DS3 signal. A high speed bit-for-bit compare is interfaced to a protect path to provide 1:1 fault protection in the system of the present invention. Full time performance monitoring on DS1 and DS3 signals is performed by a shared resource. The system of the present invention provides an integrated approach to synchronization measurement and relative synchronization.

Claims

1. In a telephone network, a method of DS3 signal access, comprising:

identifying a bit in the DS3 signal;

generating a selected bit; and

substituting the identified bit with the selected bit in the DS3 signal.

2. The system defined in claim 1, additionally comprising:

providing a regenerated DS3 signal before the substituting step; and

a DS3 transmitter providing a regenerated DS3 signal after the substituting step.

3. The method defined in claim 1, wherein the generating step includes routing the selected bit to be substituted.

4. The method defined in claim 3, wherein the generating step includes receiving the identified bit providing the selected bit to the routing step.

5. The method defined in claim 1, wherein the substituting step is synchronous to the DS3 signal.

12. The method defined in claim 1, wherein a subrate channel is inserted into the DS3 signal.

6. A method of accessing a plurality of embedded channels in a DS3 signal, the method comprising;

extracting at least one of the DS2 channels in the DS3 signal;

communicating at least one of the DS0 channels in the DS2 channel into an asynchronous time slot on a bus; and

selectively inserting data from the bus into the DS3 signal.

7. The method defined in claim 6, wherein the selectively inserting step includes overwriting at least one bit in the DS3 signal.

8. The method defined in claim 6, wherein the bus is clocked at a rate higher than any one DS0 channel.

9. The method defined in claim 6, wherein each of the asynchronous time slots is selectively assigned to any DS0 channel in any DS1 channel.

10. The method defined in claim 6, wherein a DS1 channel is inserted into the DS3 signal.

11. The method defined in claim 6, wherein a DS0 channel is inserted into the DS3 signal.

13. In a telephone network, a method of DS3 signal access, comprising:

a first circuit capable of identifying a bit in the DS3 signal;

a second circuit capable of generating a selected bit; and

a combiner capable of substituting the identified bit with the selected bit in the DS3 signal.

14. The system defined in claim 13, additionally comprising:

a DS3 receiver providing a regenerated DS3 signal to the combiner; and

a DS3 transmitter providing a regenerated DS3 signal from the combiner.

15. The system defined in claim 13, wherein the second circuit includes a DS1 signal router for routing the selected bit to the combiner.

16. The system defined in claim 15, wherein the second circuit includes a DS1 test system for receiving the identified bit and providing the selected bit to the DS1 router.

17. The system defined in claim 13, wherein the second circuit includes a DS0 signal router for routing the selected bit to the combiner.

18. The system defined in claim 17, wherein the second circuit includes a DS0 test system for receiving the identified bit and providing the selected bit to the DS0 router.

19. The system defined in claim 13, wherein the system is an integrated assembly.

20. The system defined in claim 13, wherein the combiner is synchronous to the DS3 signal.

21. A system for accessing a plurality of embedded channels in a DS3 signal, the system comprising:

a demultiplexer capable of extracting at least one of the DS2 channels in the DS3 signal;

an asynchronous time slot interchange capable of communicating at least one of the DS0 channels in the DS2 channel into an asynchronous time slot on a bus; and

an insertion circuit capable of selectively inserting data from the bus into the DS3 signal.

22. The system defined in claim 21, wherein the insertion circuit includes a circuit capable of overwriting at least one bit in the DS3 signal.

23. The system defined in claim 21, wherein the bus is clocked at a rate higher than any one DS0 channel.

24. The system defined in claim 21, wherein each of the asynchronous time slots are selectively assigned to any DS0 channel in any DS1 channel.

25. The system defined in claim 21, wherein a DS1 channel is inserted into the DS3 signal.

26. The system defined in claim 21, wherein a DS0 channel is inserted into the DS3 signal.

27. The system defined in claim 21, wherein a subrate channel is inserted into the DS3 signal.

28. The system defined in claim 21, wherein the bus includes a bit stuffing circuit capable of bit stuffing.

29. The system defined in claim 28, wherein the bit stuffing circuit includes a line for carrying valid bit data.