Built in self repair for DRAMs using on-chip temperature sensing and heating

• US 5,956,350 A
• Filed: 10/27/1997
• Issued: 09/21/1999
• Est. Priority Date: 10/27/1997
• Status: Expired due to Term

• Current Assignee: Credence Systems Corporation (COHU Incorporated), Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.), Heuristic Physics Laboratories
• Inventors: Lepejian, Yervant D., Irrinki, V. Swamy
• Primary Examiner(s): Canney, Vincent P.
• Application Number:
  US08/958,775
• Time in Patent Office: 694 Days
• Field of Search: 371/21.1, 371/21.2, 371/21.4, 371/21.6, 371/22.1, 371/22.5, 371/28, 365/201, 395/183.18
• US Class Current: 714/718
• CPC Class Codes: G01R 31/3173 Marginal testing
• CPC Class Codes: G11C 11/401 forming cells needing refreshing or charge regeneration, i.e. dynamic cells
• CPC Class Codes: G11C 2029/5002 Characteristic
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: G11C 29/50016 of retention

Abstract

A memory device which tests the memory array under typical operating conditions. In one embodiment, the memory device incorporates a heating element to heat the memory array to a predetermined operating temperature, and a BIST (built-in self test) unit to test the memory array at the predetermined operating temperature. This may advantageously provide a method for detecting and repairing faulty memory locations that would not normally test faulty under initial power-up conditions. Broadly speaking, the present invention contemplates a memory device which comprises a memory array and a heating element on a substrate. The memory array is configured to receive a read/write signal on a read/write line, configured to receive an address on an address bus, configured to provide data to a data bus when the read/write signal indicates a read operation, and configured to store data from the data bus when the read/write signal indicates a write operation. The data on the data bus is stored in a memory location indicated by the address on the address bus. The heating element is coupled to the substrate to heat the memory array to a predetermined operating temperature. The memory device may further include a temperature sensor coupled to the substrate and configured to provide a temperature signal indicative of a temperature of the memory array, and a heating control coupled to receive the temperature signal and coupled to responsively regulate power to the heating element.

Claims

1. A memory device which comprises:

a memory array on a substrate, wherein the memory array is configured to a receive a read/write signal on a read/write line, configured to receive an address on an address bus, configured to provide data to a data bus when the read/write signal indicates a read operation, and configured to store data from the data bus when the read/write signal indicates a write operation, wherein the data on the data bus is stored in a memory location indicated by the address; and

a heating element coupled to the substrate to heat the memory array to a predetermined operating temperature.

2. The memory device of claim 1, further comprising:

a temperature sensor coupled to the substrate and configured to provide a temperature signal indicative of a temperature of the memory array; and

a heating control coupled to receive the temperature signal and coupled to responsively provide power to the heating element.

3. The memory device of claim 2, wherein the heating control is configured to begin providing power to the heating element when the memory device is powered on, and wherein the heating control is configured to stop providing power to the heating element when the temperature signal is indicative of the predetermined operating temperature.

4. The memory device of claim 1, further comprising a BIST (built-in self test) unit coupled to provide the read/write signal on the read/write line, coupled to provide the address on the address line, and coupled to provide and receive data on the data bus, wherein the BIST unit is configured to generate test patterns and apply the test patterns to the memory array to test for faulty memory locations after the memory array has been heated to the predetermined operating temperature.

5. The memory unit of claim 4, further comprising a BISR (built-in self repair) module coupled to receive a detected faulty memory location from the BIST unit, and coupled to the address line to store the address of the detected faulty memory location, wherein the BISR module is configured to intercept subsequent accesses to the detected faulty memory location and reroute the accesses to a redundant memory location.

6. The memory unit of claim 4, further comprising:

a temperature sensor coupled to the substrate and configured to provide a temperature signal indicative of a temperature of the memory array; and

a refresh interval lookup table coupled to receive the temperature signal and configured to responsively provide a refresh interval to the BIST unit.

7. A method for on-chip testing and repairing of memories in a system that contains a heating element, a test circuit, a repair circuit, a memory array, and a plurality of redundant memory locations within the memory array, the method comprising the steps of:

heating the memory array to a predetermined operating temperature;

testing the memory array;

determining an original address of a faulty location in the memory array; and

repairing the faulty location by using the repair circuit to redirect the original address to an address of a redundant memory location.

8. The method of claim 7, wherein the heating step includes:

applying power to the heating element at system power-on;

sensing a temperature of the memory array with a temperature sensor; and

discontinuing the power to the heating element when the temperature of the memory array approaches the predetermined operating temperature.

9. The method of claim 8, wherein said testing step includes:

obtaining a data retention test interval;

generating a test pattern;

applying the test pattern to the memory array; and

comparing data from the memory array to expected results.

10. The method of claim 9, wherein the obtaining step includes:

receiving a temperature signal from the temperature sensor; and

providing the temperature signal to a lookup table.

11. The method of claim 10, further comprising the steps, prior to the repairing step, of:

storing the original address; and

translating the original address to the address of the redundant memory location.

12. An on-chip system for detecting and repairing data retention faults under normal operating conditions, wherein the system comprises:

a memory array including a plurality of memory cells;

a plurality of redundant memory cells coupled to the memory array for replacing faulty memory cells;

a heating element coupled to the memory array for heating the memory array to a predetermined operating temperature;

a testing unit coupled to the memory array for testing the memory array and determining an original address of a faulty memory cell; and

a repair module coupled to the memory array and the testing unit for repairing the faulty memory cell with a redundant memory cell by redirecting the original address to an address of the redundant memory cell.

13. The system of claim 12, further comprising:

a temperature sensor coupled to the memory array, and configured to provide a temperature signal indicative of a temperature of the memory array; and

a heating control configured to provide power to the heating element when the system is powered-on, and configured to discontinue powering the heating element when the temperature signal is indicative of the predetermined operating temperature.

14. The system of claim 13, further comprising a lookup table coupled to receive the temperature signal and configured to provide a refresh interval to the testing unit.

15. The system of claim 14, wherein the testing unit is configured to test the memory array to detect data retention faults after the memory array has been heated to the predetermined operating temperature.

16. An on-chip system for detecting and repairing data retention faults, wherein the system comprises:

a memory array including a plurality of memory cells;

a plurality of redundant memory cells coupled to the memory array for replacing faulty memory cells;

a heating element coupled to the memory array for heating the memory array;

a testing unit coupled to the memory array for testing the memory array and determining an original address of a faulty memory cell; and

a repair module coupled to the memory array and the testing unit for repairing the faulty memory cell with a redundant memory cell by redirecting the original address to an address of the redundant memory cell.

17. The system of claim 16, further comprising a heating control configured to provide power to the heating element when the system is powered-on, and configured to discontinue powering the heating element after a predetermined time interval has elapsed.

18. The system of claim 17, wherein the testing unit is configured to test the memory array to detect data retention faults after the heating control has discontinued powering the heating element.