Fault resilient/fault tolerant computing

• US 5,956,474 A
• Filed: 12/18/1996
• Issued: 09/21/1999
• Est. Priority Date: 12/01/1993
• Status: Expired due to Term

• Current Assignee: Stratus Technologies Bermuda Ltd. (Stratus Technologies Bermuda Holdings Ltd.)
• Original Assignee: Marathon Technologies Corporation (Stratus Technologies Bermuda Holdings Ltd.)
• Inventors: Tremblay, Glenn A., McCollum, James D., Glorioso, Robert M., Bissett, Thomas Dale, Troiani, Mario, McCauley, Diane T., Fiorentino, Richard D.
• Primary Examiner(s): PALYS, JOSEPH E
• Application Number:
  US08/768,437
• Time in Patent Office: 1,007 Days
• Field of Search: 395/182.02, 395/182.09, 395/182.08, 395/182.1, 395/182.11, 395/185.1, 395/183.01, 395/183.08, 395/183.16, 395/183.2
• US Class Current: 714/11
• CPC Class Codes: G06F 1/14 Time supervision arrangements, e.g. real time clock
• CPC Class Codes: G06F 11/1641 where the comparison is not performed by the redundant processing components
• CPC Class Codes: G06F 11/1645 and the comparison itself uses redundant hardware
• CPC Class Codes: G06F 11/1658 Data re-synchronization of a redundant component, or initial sync of replacement, additional or spare unit
• CPC Class Codes: G06F 11/1683 at instruction level
• CPC Class Codes: G06F 11/1687 at event level, e.g. by interrupt or result of polling
• CPC Class Codes: G06F 11/1691 using a quantum
• CPC Class Codes: G06F 11/181 Eliminating the failing redundant component
• CPC Class Codes: G06F 11/185 and the voting is itself performed redundantly
• CPC Class Codes: G06F 11/2005 using redundant communication controllers
• CPC Class Codes: G06F 11/2017 where memory access, memory control or I/O control functionality is redundant redundant communication control functionality G06F11/2005; redundant storage control functionality G06F11/2089

Abstract

Fault resilient or fault tolerant computers are produced by designating a first processor as a computing element, designating a second processor as a controller, connecting the computing element and the controller to produce a modular pair, and connecting at least two module pairs to produce a fault resilient or fault tolerant computer. Each computing element of the computer performs all instructions in the same number of cycles as the other computing element. The controllers provide input/output processings for the computing elements, as well as monitor their operations to detect errors, and control operation of the computing elements in response to the detected errors.

Claims

1. A method of producing a fault resilient or fault tolerant computer, comprising:

designating a first processor as a computing element;

configuring the computing element to run an application program;

designating a second processor as a controller;

configuring the controller to monitor operation of the computing element to detect errors in the operation of the computing element, to control operation of the computing element in response to detected errors, and to provide input/output processing for the computing element;

connecting the computing element and the controller to produce a modular pair;

connecting at least two modular pairs to produce a fault resilient or fault tolerant computer,

wherein each computing element performs all instructions in the same number of cycles as the other computing elements.

2. The method of claim 1, wherein the first and second processors are industry standard processors.

3. The method of claim 1, further comprising running industry standard operating systems and applications on the at least two controllers and the at least two computing elements.

4. The method of claim 1, further comprising:

running a first operating system on the at least two controllers; and

running a second, different system on the at least two computing elements.

5. The method of claim 1, further comprising locating a modular pair remotely from the one or more other modular pairs to provide disaster tolerance.

6. The method of claim 1, further comprising:

connecting a first I/O device to a first modular pair;

connecting a second I/O device to a second modular pair, said second I/O device being redundant of the first I/O device; and

transmitting at least identical I/O write requests and data to the first and second I/O devices.

7. The method of claim 6, further comprising:

connecting a third I/O device to a third modular pair, said third I/O device being redundant of the first and second I/O devices; and

transmitting at least identical I/O write requests and data to the first, second, and third I/O devices.

8. The method of claim 1, further comprising activating an inactive processor by transferring the operational state of an active processor to the inactive processor through a controller.

9. The method of claim 8, further comprising pausing processing by said computing elements while transferring the operational state.

10. The method of claim 8, further comprising performing said transfer of the operational state as a background process without pausing processing by said computing elements.

11. The method of claim 1, further comprising upgrading a processor while said computing elements are processing by:

disabling a processor to be upgraded;

upgrading the disabled processor; and

reactivating the upgraded processor by transferring the operational state of an active processor to the upgraded processor through a controller.

12. The method of claim 1, further comprising repairing a processor while said computing elements are processing by:

disabling a processor to be repaired;

repairing the disabled processor; and

reactivating the repaired processor by transferring the operational state of an active processor to the repaired processor through a controller.

13. The method of claim 1, further comprising configuring all computing elements to run identical application programs.

14. The method of claim 13, wherein monitoring operation of the computing element comprises monitoring input/output requests made by the computing element.

15. The method of claim 14, wherein monitoring operation of the computing element further comprises comparing input/output requests made by the computing element to input/output requests made by other computing elements and indicating the occurrence of an error when the input/output requests for two computing elements do not match.