Intermediate-grain reconfigurable processing device

• US 5,956,518 A
• Filed: 04/11/1996
• Issued: 09/21/1999
• Est. Priority Date: 04/11/1996
• Status: Expired due to Fees

• Current Assignee: Massachusetts Institute of Technology
• Original Assignee: Massachusetts Institute of Technology
• Inventors: DeHon, Andre, Knight, Thomas F. Jr., Mirsky, Ethan
• Primary Examiner(s): Coleman, Eric
• Application Number:
  US08/632,371
• Time in Patent Office: 1,258 Days
• Field of Search: 395/800.1, 395/800.15, 395/200.51, 395/280, 395/653
• US Class Current: 712/15
• CPC Class Codes: G06F 15/8023 Two dimensional arrays, e.g. mesh, torus

Abstract

A programmable integrated circuit utilizes a large number of intermediate-grain processing elements which are multibit processing units arranged in a configurable mesh. The coarse-grain resources, such as memory and processing, are deployable in a way that takes advantage of the opportunities for optimization present in given problems. To accomplish this, the interconnect supports three different modes of operation: a static value in which a value set by the configuration data is provided to a functional unit, static source in which another functional unit serves as the value source, and a dynamic source mode in which the source is determined by the value from another functional unit.

Claims

1. A programmable integrated circuit comprising:

logic units which perform operations on data in response to instructions of a defined set of instructions;

memories which store and retrieve data in response to received addresses;

a configurable interconnect which provides signal transmission between the logic units and memories, the interconnect being configurable from configuration control data to define data paths, originating at logic units and/or memories, through the interconnect as address inputs to memories, data inputs to memories and logic units, and instruction inputs to logic units such that the interconnect is configurable to define an interdependent functionality of the memories and logic units; and

programmable configuration storage for storing the configuration control data.

2. An integrated circuit as claimed in claim 1 wherein at least one memory provides at least part of the instructions to a logic unit.

3. An integrated circuit as claimed in claim 1 wherein the logic units are configurable to receive data directly from associated memories.

4. An integrated circuit as claimed in claim 1 wherein the configuration storage stores multiple contexts of configuration control data for reconfiguration of the programmable interconnect.

5. An integrated circuit as claimed in claim 4 wherein a context selection signal that selects among the multiple contexts is routed by the configurable interconnect.

6. An integrated circuit as claimed in claim 5 wherein a global context selection signal that selects among the multiple contexts is globally broadcast to the programmable configuration storage of the device.

7. An integrated circuit as claimed in claim 1 wherein the interconnect is configurable to provide a static value to a logic unit or to provide a variable value from a static source.

8. An integrated circuit as claimed in claim 1 wherein the memories are deployable as data memory, register files, program counters, and instruction stores for other logic units.

9. An integrated circuit as claimed in claim 1 wherein the interconnect comprises network drivers which transmit received signals between the memories and logic units.

10. A programmable integrated circuit comprising:

logic units which perform operations on data in response to instructions of a defined set of instructions;

memories which store and retrieve data in response to received addresses;

a configurable interconnect which provides signal transmission between the logic units and memories, the interconnect being configurable from configuration control data to define data paths through the interconnect as address inputs to memories, data inputs to memories and logic units, and instruction inputs to logic units such that the interconnect is configurable to define an interdependent functionality of the memories and logic units; and

programmable configuration storage for storing the configuration control data;

wherein a global context selection signal that selects among multiple contexts is globally broadcast to the programmable configuration storage of the device.

11. A programmable integrated circuit comprising:

logic units which perform operations on data in response to instructions of a defined set of instructions and which are configurable to be chained together to form wider data paths than provided by a single logic unit;

memories which store and retrieve data in response to received addresses;

a configurable interconnect which provides signal transmission between the logic units and memories, the interconnect being configurable from configuration control data to define data paths through the interconnect as address inputs to memories, data inputs to memories and logic units, and instruction inputs to logic units such that the interconnect is configurable to define an interdependent functionality of the memories and logic units; and

programmable configuration storage for storing the configuration control data.

12. A programmable integrated circuit comprising:

logic units which perform operations on data in response to instructions of a defined set of instructions;

memories which store and retrieve data in response to received addresses;

a configurable interconnect which provides signal transmission between the logic units and memories, the interconnect being configurable from configuration control data to define data paths through the interconnect as address inputs to memories, data inputs to memories and logic units, and instruction inputs to logic units such that the interconnect is configurable to define an interdependent functionality of the memories and logic units, the interconnect being configurable to provide a value to a logic unit or memory from a source, which is determined by a value from another logic unit or memory; and

programmable configuration storage for storing the configuration control data.

13. A programmable integrated circuit comprising:

logic units which perform operations on data in response to instructions of a defined set of instructions;

memories which store and retrieve data in response to received addresses, the logic units being each grouped with memories to form repeating functional units;

a configurable interconnect which provides signal transmission between the logic units and memories, the interconnect being configurable from configuration control data to define data paths through the interconnect as address inputs to memories, data inputs to memories and logic units, and instruction inputs to logic units such that the interconnect is configurable to define an interdependent functionality of the memories and logic units; and

programmable configuration storage for storing the configuration control data.

14. An integrated circuit as claimed in claim 13 further comprising programmable logic arrays on data paths between functional units which perform bit level logic operations.

15. An integrated circuit as claimed in claim 13 further comprising reduction logic which performs logic operations on the output of the logic units and passes a result to other functional units as control information.

16. An integrated reconfigurable computing device, comprising:

an array of functional units comprising;

multibit arithmetic logic units which perform operations on data in response to instructions;

memories which store and retrieve data in response to received addresses;

function switches which determine the source of the instructions to the logic units; and

address/data switches which are configurable by the other functional units and determine the source of addresses to the memories and the source of data to the logic units and memories.

17. An integrated circuit as claimed in claim 16 wherein the logic units are configurable to both operate on data from the associated memories and operate on data received from outside the functional unit via the address/data switches.

18. An integrated circuit as claimed in claim 16 wherein the function switches also determine the configuration of the memories.

19. An integrated circuit as claimed in claim 16 wherein the address/data switches are configurable to provide static values, values from other functional units, and values from sources, which are determined by other functional units.

20. An integrated circuit as claimed in claim 16 wherein in the output from the arithmetic logic units are distributed over a local network to near-neighbor functional units.

21. An integrated circuit as claimed in claim 16 wherein the functional units comprise network drivers which transmit received signals to other functional units.

22. An integrated circuit as claimed in claim 21 wherein sources of the received signals to the network drivers are programmable by other functional units.

23. A method for organizing signal transmission within an array of logic units which perform operations on data in response to instructions and memories which store and retrieve data in response to received addresses, the method comprising:

transmitting data read from the memories as instructions or data to the logic units or addresses or data to other memories; and

transmitting data generated by the logic units as instructions or data to other logic units or addresses or data to the memories.

24. A method as claimed in claim 23 further comprising transmitting data from logic units or memories as control to other logic units or memories.

25. A method as claimed in claim 23 further comprising reorganizing the paths of the data and instructions in response to control from the array.

26. A method as claimed in claim 23 further comprising transmitting static values, values from other memories or logic units, and values from sources determined by the memories or logic units.

27. A method as claimed in claim 23 further comprising performing bit level logic operations to control data paths between memories or logic units.

28. A method as claimed in claim 23 further comprising selecting among multiple contexts using a globally broadcast context selection signal to the programmable configuration storage of the device.

29. A method as claimed in claim 23 further comprising configuring the logic units to be chained together to form wider data paths than provided by a single logic unit.

30. A method as claimed in claim 23 further comprising providing a value to a logic unit or memory from a source, which is determined by a value from another logic unit or memory.

31. A method as claimed in claim 23 further comprising grouping each of the logic units with memories to form repeating functional units.