Picture end token in a system comprising a plurality of pipeline stages

• US 5,956,519 A
• Filed: 05/01/1997
• Issued: 09/21/1999
• Est. Priority Date: 06/30/1992
• Status: Expired due to Term

• Current Assignee: Coases Investments Bros LLC (Intellectual Ventures LLC)
• Original Assignee: Discovision Associates (Pioneer Corporation)
• Inventors: Wise, Adrian Philip, Sotheran, Martin William
• Primary Examiner(s): Donaghue, Larry D.
• Assistant Examiner(s): Davis, Jr., Walter D.
• Application Number:
  US08/850,125
• Time in Patent Office: 873 Days
• Field of Search: 395/800.01, 395/800.16, 395/800.18, 395/376, 395/377, 395/500
• US Class Current: 712/16
• CPC Class Codes: G06F 12/0207 with multidimensional access, e.g. row/column, matrix
• CPC Class Codes: G06F 12/04 Addressing variable-length words or parts of words
• CPC Class Codes: G06F 12/0607 Interleaved addressing
• CPC Class Codes: G06F 13/16 for access to memory bus G06F13/28 takes precedence
• CPC Class Codes: G06F 13/1673 using buffers
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 9/3867 using instruction pipelines
• CPC Class Codes: G06F 9/4494 data driven
• CPC Class Codes: H04N 19/13 Adaptive entropy coding, e.g. adaptive variable length coding [AVLC] or context adaptive binary arithmetic coding [CABAC]
• CPC Class Codes: H04N 19/42 characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation H04N19/635 takes precedence
• CPC Class Codes: H04N 19/423 characterised by memory arrangements H04N19/433 takes precedence
• CPC Class Codes: H04N 19/61 in combination with predictive coding
• CPC Class Codes: H04N 19/91 Entropy coding, e.g. variable length coding [VLC] or arithmetic coding

Abstract

A multi-standard video decompression apparatus has a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and data in token format. A token decode circuit is positioned in certain of the stages for recognizing certain of the tokens as control tokens pertinent to that stage and for passing unrecognized control tokens along the pipeline. Reconfiguration processing circuits are positioned in selected stages and are responsive to a recognized control token for reconfiguring such stage to handle an identified DATA Token. A wide variety of unique supporting subsystem circuitry and processing techniques are disclosed for implementing the system.

Claims

1. For use with a system having a plurality of processing stages:

a universal adaptation unit in the form of an interactive interfacing token for control and/or data functions among said processing stages, said token being transmitted from one of said processing stages to an immediately succeeding processing stage along a data flow path, and said token incorporating an extension bit, wherein sequential processing stages are connected by two-wire interfaces, and further comprising;

electrical validation circuitry in at least one processing stage to generate a validation signal for a first state when data stored in said stage is valid and for a second state when data stored in said stage is invalid, said state defining said stage'"'"'s ability to accept data, said validation circuitry including at least one validation storage device to store said validation signal for the corresponding pipeline stage;

an acceptance signal connecting an adjacent pair of processing stages and conveying an acceptance signal indicative of the ability of said successive pipeline stage to load data stored in the preceding pipeline stage; and

enabling circuitry connected to said data storage devices for generating an enabling signal to enable loading of data and validation signals into the respective storage devices, wherein;

said data storage devices include a primary data storage device and a secondary data storage device;

said data is loaded into said respective primary data storage devices and said validation signal is loaded into a respective primary validation storage device at the same time;

data is loaded into said respective primary data storage device when said acceptance signal assumes an enabling state; and

said acceptance signal assumes said enabling state only when the acceptance signal associated with the data storage device of said next successive pipeline stage is in said enabling state or said data in said data storage device of said next successive pipeline stage is invalid;

wherein said token is a PICTURE_-- END token for indicating the end of an individual picture.

2. The arrangement according to claim 1 wherein said token is Huffman coded.

3. The arrangement according to claim 1, wherein the PICTURE_-- END token is transmitted in said data flow path following picture information of variable length.

4. The arrangement according to claim 3, wherein said picture information is encoded according to an H.261 format.

5. The arrangement according to claim 3, wherein said picture information is encoded according to a JPEG format.

6. The arrangement according to claim 3, wherein said picture information is encoded according to an MPEG format.

7. The arrangement according to claim 1, wherein said token includes an extension bit.

8. In a system having an input, an output and a plurality of processing stages between the input and the output, the improvement characterized by:

an interactive metamorphic interfacing token, defining a universal adaptation unit for control and/or data functions among said processing stages, said token being transmitted from one of said processing stages to an immediately succeeding processing stage along a data flow path, and said token incorporating an extension bit, wherein sequential processing stages are connected by two-wire interfaces, and further comprising;

electrical validation circuitry in at least one processing stage to generate a validation signal for a first state when data stored in said stage is valid and for a second state when data stored in said stage is invalid, said state defining said stage'"'"'s ability to accept data, said validation circuitry including at least one validation storage device to store said validation signal for the corresponding pipeline stage;

an acceptance signal connecting an adjacent pair of processing stages and conveying an acceptance signal indicative of the ability of said successive pipeline stage to load data stored in the preceding pipeline stage; and

enabling circuitry connected to said data storage devices for generating an enabling signal to enable loading of data and validation signals into the respective storage devices,

wherein;

said data storage devices include a primary data storage device and a secondary data storage device;

said data is loaded into said respective primary data storage devices and said validation signal is loaded into a respective primary validation storage device at the same time;

data is loaded into said respective primary data storage device when said acceptance signal assumes an enabling state; and

said acceptance signal assumes said enabling state only when the acceptance signal associated with the data storage device of said next successive pipeline stage is in said enabling state or said data in said data storage device of said next successive pipeline stage is invalid;

wherein said token is a PICTURE_-- END token for indicating the end of an individual picture.

9. The arrangement according to claim 8 wherein said token is Huffman coded.

10. The arrangement according to claim 8, wherein the PICTURE_-- END token is transmitted in said data flow path following picture information of variable length.

11. The arrangement according to claim 10 wherein said picture information is encoded according to an H.261 format.

12. The arrangement according to claim 10 wherein said picture information is encoded according to a JPEG format.

13. The arrangement according to claim 10 wherein said picture information is encoded according to an MPEG format.

14. The arrangement according to claim 8, wherein said token includes an extension bit.