Method of fabricating vertical FET with Schottky diode

• US 5,956,578 A
• Filed: 04/23/1997
• Issued: 09/21/1999
• Est. Priority Date: 04/23/1997
• Status: Expired due to Fees

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Weitzel, Charles E., Bhatnagar, Mohit, Thero, Christine
• Primary Examiner(s): Nguyen, Tuan H.
• Application Number:
  US08/839,226
• Time in Patent Office: 881 Days
• Field of Search: 438/173, 438/176, 438/186, 438/192, 438/135, 438/136, 438/137, 438/138, 438/570, 257/135, 257/195, 257/267, 257/263, 257/328, 257/280, 257/476
• US Class Current: 438/138
• CPC Class Codes: H01L 27/0605 integrated circuits made of compound material, e.g. AIIIBV

Abstract

A method of fabricating an integrated VFET and Schottky diode including forming a source region on the upper surface of a substrate so as to define a channel. First and second spaced apart gates are formed on opposing sides of the source region so as to abut the channel, thereby forming a channel structure. Schottky metal is positioned on the upper surface of the substrate proximate the channel structure to define a Schottky diode region and form a Schottky diode. A source contact is formed in communication with the source region and the Schottky metal, and a drain contact is formed on the lower surface of the substrate.

Claims

1. A method of fabricating an integrated vertical field effect transistor and Schottky diode comprising the steps of:

providing a substrate having a first surface and an opposed second surface;

forming a source region on the first surface of the substrate so as to define a channel therebelow;

forming first and second spaced apart gates on opposing sides of the source region so as to abut the channel thereby forming a channel structure;

positioning Schottky metal on the first surface of the substrate proximate the channel structure to define a Schottky diode region and form a Schottky diode;

forming a source contact in communication with the source region and the Schottky metal; and

forming a drain contact on the second surface of the substrate.

2. A method as claimed in claim 1 wherein the step of providing the substrate includes providing a substrate selected from a group including GaAs, SiC, GaN and InP.

3. A method as claimed in claim 1 wherein the step of forming the source contact includes using Schottky metal.

4. A method as claimed in claim 1 wherein the step of forming the channel includes forming the channel with a current rating, and the step of forming the Schottky diode includes forming the Schottky diode with a current rating 0.1-0.2 times the current rating of the channel.

5. A method as claimed in claim 1 further including the step of forming a field plate in communication with the source on the first surface of the substrate and extending toward the Schottky diode.

6. A method as claimed in claim 1 wherein the steps of forming the gates and source region further comprise the steps of:

implanting a source species to form the source region in the first surface of the substrate;

forming first and second spaced apart gate trenches, each having sidewalls and a bottom, in the first surface of the substrate on opposing sides of the source region so as to define the channel underlying the source region;

co-implanting carbon and a lattice damaging species to form gates in the bottoms of the first and second trenches; and

forming gate contacts in communication with the gates.

7. A method of fabricating an integrated vertical field effect transistor and Schottky diode comprising the steps of:

providing a substrate having a first surface and an opposed second surface selected from a group including GaAs, SiC, GaN and InP;

implanting a source species to form a source region in the first surface of the substrate so as to define a channel therebelow;

forming first and second spaced apart gates on opposing sides of the source region so as to abut the channel thereby forming a channel structure;

positioning Schottky metal on the first surface of the substrate proximate the channel structure to define a Schottky diode region and form a Schottky diode;

forming a source contact in communication with the source region and the Schottky metal; and

forming a drain contact on the second surface of the substrate.

8. A method as claimed in claim 7 wherein the step of forming first and second gates includes the steps of:

forming first and second spaced apart gate trenches, each having sidewalls and a bottom, in the first surface of the substrate on opposing sides of the source region so as to define the channel underlying the source region;

co-implanting carbon and a lattice damaging species to form gates in the bottoms of the first and second trenches; and

forming gate contacts in communication with the gates.

9. A method as claimed in claim 7 wherein the step of forming first and second gates includes the step of implanting first and second spaced apart gates on opposing sides of the source region so as to define the channel underlying the source region.

10. A method as claimed in claim 7 wherein the step of forming the source contact includes using Schottky metal.

11. A method as claimed in claim 7 wherein the step of forming the channel structure includes forming the channel structure with a current rating, and the step of forming the Schottky diode includes forming the Schottky diode with a current rating 0.1-0.2 times the current rating of the channel structure.

12. A method as claimed in claim 7 further including the step of forming a field plate in communication with the source on the first surface of the substrate and extending toward the Schottky diode.

13. A method of fabricating a plurality of integrated vertical field effect transistors and a Schottky diode comprising the steps of:

providing a substrate having a first surface and an opposed second surface;

forming a plurality of spaced apart source regions on the first surface of the substrate, each source region defining a channel therebelow;

forming a plurality of spaced apart gates, each source region having a gate on opposing sides of the source region so as to abut the channel;

positioning Schottky metal on the first surface of the substrate to define a Schottky diode;

forming a source contact in communication with the source region and the Schottky metal; and

forming a drain contact on the second surface of the substrate.

14. A method as claimed in claim 13 wherein the step of providing the substrate includes providing a substrate selected from a group including GaAs, SiC, GaN and InP.

15. A method as claimed in claim 13 wherein the step of forming spaced apart source regions includes forming the channel with a current rating, and the step of positioning Schottky metal includes forming the Schottky diode with a current rating 0.1-0.2 times the current rating of the channel.

16. A method as claimed in claim 13 wherein the steps of forming the gates and source regions further comprise the steps of:

implanting a source species to form the source regions in the first surface of the substrate;

forming a plurality of spaced apart gate trenches, each having sidewalls and a bottom, in the first surface of the substrate, each of the source regions having a gate trench on opposing sides so as to define the channel underlying the source region;

co-implanting carbon and a lattice damaging species to form gales in the bottoms of each of the plurality of trenches; and

forming a plurality of gate contacts, each in communication with a gate.