Interface for connecting a bus to a random access memory using a swing buffer and a buffer manager

• US 5,956,741 A
• Filed: 10/15/1997
• Issued: 09/21/1999
• Est. Priority Date: 03/24/1994
• Status: Expired due to Term

• Current Assignee: Coases Investments Bros LLC (Intellectual Ventures LLC)
• Original Assignee: Discovision Associates (Pioneer Corporation)
• Inventors: Jones, Anthony Mark
• Primary Examiner(s): Chan, Eddie P.
• Assistant Examiner(s): Verbrug, Kevin
• Application Number:
  US08/950,892
• Time in Patent Office: 706 Days
• Field of Search: 711/1, 711/200, 348/446, 348/398, 364/238.6, 364/239, 364/926.3, 364/926.6
• US Class Current: 711/1
• CPC Class Codes: G06F 12/0207 with multidimensional access, e.g. row/column, matrix
• CPC Class Codes: G06F 12/04 Addressing variable-length words or parts of words
• CPC Class Codes: G06F 12/0607 Interleaved addressing
• CPC Class Codes: G06F 13/16 for access to memory bus G06F13/28 takes precedence
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: H04N 19/13 Adaptive entropy coding, e.g. adaptive variable length coding [AVLC] or context adaptive binary arithmetic coding [CABAC]
• CPC Class Codes: H04N 19/423 characterised by memory arrangements H04N19/433 takes precedence
• CPC Class Codes: H04N 19/61 in combination with predictive coding
• CPC Class Codes: H04N 19/91 Entropy coding, e.g. variable length coding [VLC] or arithmetic coding

Abstract

A configurable RAM interface connecting a bus to RAM is adapted to receiving large multiword variable length tokens at a high data arrival rate, using a swing buffer and a buffer manager. An address source provides complete addresses to the interface. The buffer manager has a state machine which transitions among a plurality of states, maintaining status information about the buffers, allocating the buffers for reference by a write address generator, clearing the buffers for occupation by subsequently arriving data, and maintaining status information concerning the buffers. The buffer manager also examines tokens of received data in order to update the status of the arrival buffer.

Claims

1. A configurable RAM interface for connecting a bus to RAM comprising:

a bus configuration register for specifying a number of bits on the bus;

means for receiving from the bus a plurality of data words comprising multiword tokens;

means for receiving from the bus a complete address associated with the plurality of data words;

means for generating a series of addresses in RAM into which the buffered data words will be written;

means for writing the buffered data words into RAM at the generated addresses; and

means for buffering the received data words comprising;

at least three memory buffers for use as a swing buffer including an arrival buffer, an output buffer and at least one intermediate buffer;

a buffer manager for allocating said buffers for reference by said means for generating a series of addresses, clearing said buffers for occupation by subsequently arriving data, and maintaining status information of said buffers, wherein said status information comprises a state VACANT, wherein one of said buffers is available, a state IN_-- USE, wherein said one buffer is referenced by said means for receiving from the bus an address and by said means for receiving from the bus a plurality of data words, a state FULL, wherein said one buffer is occupied by data, and a state READY wherein said buffer manager asserts a late arrival signal indicating that a buffer in said state READY is not in synchronization with a data output rate;

a state machine in said buffer manager that transitions among a plurality of states, the transitions including;

a first transition from a first state PRES0, to a second state PRES1, wherein said status information of said buffers are evaluated;

a second transition from said state PRES1 to a third state DRQ wherein a pending request for said output buffer is evaluated; and

a third transition from said state DRQ to a fourth state TOKEN, wherein tokens of received data are examined;

whereby a status of said arrival buffer can be updated.

2. The RAM interface of claim 1 wherein:

the RAM operates in page addressing mode; and

the address generating means includes means for generating row addresses, and means for generating column addresses based on the received address.

3. The RAM interface of claim 2, wherein:

the RAM is a DRAM;

a first two wire interface is disposed between said bus and said address receiving means;

the data word receiving and buffering means includes a second two wire interface;

wherein said first two wire interface, and said second two wire interface each comprise;

a sender, a receiver, and a clock connected to said sender and said receiver, wherein data is transferred from said sender to said receiver upon a transition of said clock only when said sender is ready and said receiver is ready.

4. The RAM interface of claim 1 further including means for determining whether the data word receiving means has received and buffered the plurality of data words.

5. The interface according to claim 1, further comprising an on-chip phase lock loop circuit for generating clock signals.

6. The interface according to claim 1, wherein said tokens each comprise a plurality of data words, said data words each including an extension bit which indicates a presence of additional words in said token.

7. A RAM interface for connecting a bus to RAM comprising:

a plurality of data words stored in RAM at predetermined addresses;

means for receiving from the bus a RAM address associated with the plurality of data words;

means for generating a series of complete RAM addresses for addressing the plurality of data words in RAM, the series of addresses being derived from the received address;

means for buffering the data words read from RAM comprising;

at least three memory buffers for use as a swing buffer including an arrival buffer;

an output buffer, and at least one intermediate buffer;

a buffer manager for allocating said buffers for reference by said means for generating a series of addresses, clearing said buffers for occupation by subsequently arriving data, and maintaining status information of said buffers, wherein said status information comprises a state VACANT, wherein one of said buffers is available, a state IN_-- USE, wherein said one buffer is referenced by said means for receiving from the bus an address and by said means for receiving from the bus a plurality of data words, a state FULL, wherein said one buffer is occupied by data, and a state READY wherein said buffer manager asserts a late arrival signal indicating that a buffer in said state READY is not in synchronization with a data output rate;

a state machine in said buffer manager that transitions among a plurality of states, the transitions including;

a first transition from a first state PRES0, to a second state PRES1, wherein said status information of said buffers are evaluated;

a second transition from said state PRES1 to a third state DRQ wherein a pending request for said output buffer is evaluated; and

a third transition from said state DRQ to a fourth state TOKEN, wherein variable length tokens of received data are examined;

whereby a status of said arrival buffer can be updated; and

means for reading from RAM the plurality of data words, using the series of RAM addresses generated by the address generating means, and writing the data words into the buffer means;

wherein said data words each include an extension bit which indicates a presence of additional words to define said variable length tokens.

8. The RAM interface of claim 7 wherein:

the RAM operates in page addressing mode; and

the address generating means includes means for generating row addresses, and means for generating column addresses based on the received address.

9. The RAM interface of claim 8, wherein:

the RAM is a DRAM;

a first two wire interface is disposed between said bus and said address receiving means;

the data word receiving and buffering means includes a second two wire interface;

wherein said first two wire interface and said second two wire interface each comprise;

a sender, a receiver, and a clock connected to said sender and said receiver, wherein data is transferred from said sender to said receiver upon a transition of said clock only when said sender is ready and said receiver is ready.

10. The RAM interface of claim 7 further including means for determining whether the data word receiving means has received and buffered the plurality of data words.