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Transparent management at host interface of flash-memory overhead-bytes using flash-specific DMA having programmable processor-interrupt of high-level operations

  • US 5,956,743 A
  • Filed: 09/29/1997
  • Issued: 09/21/1999
  • Est. Priority Date: 08/25/1997
  • Status: Expired due to Term
First Claim
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1. A flash-memory system that transparently manages system-overhead bytes, the flash-memory system comprising:

  • a plurality of non-volatile flash-memory chips, each flash-memory chip storing a plurality of blocks of pages, each page having a data portion and system-overhead bytes for the page;

    a direct-memory access (DMA) controller for accessing the flash-memory chips by generating commands to the flash-memory chips;

    a volatile cache memory for storing pages of data transferred from the flash-memory chips by the DMA controller, the volatile cache memory organized to store the system-overhead bytes for a page with the data portion of the page;

    a host interface for receiving commands from a host and for transferring data to the host from the flash-memory system; and

    an overhead-byte generator, coupled to the host interface, for appending dummy overhead bytes to each page of data from the host, the dummy overhead bytes written to the volatile cache memory as the system-overhead bytes when the data portion of the page is transferred from the host to the volatile cache memory, the overhead-byte generator including stripping means for removing the system-overhead bytes from the page when the page is transferred from the volatile cache memory to the host interface for reading by the host,whereby the system-overhead bytes are stored in the volatile cache memory and in the flash-memory chips but not transferred to or from the host.

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