Transparent management at host interface of flash-memory overhead-bytes using flash-specific DMA having programmable processor-interrupt of high-level operations
First Claim
1. A flash-memory system that transparently manages system-overhead bytes, the flash-memory system comprising:
- a plurality of non-volatile flash-memory chips, each flash-memory chip storing a plurality of blocks of pages, each page having a data portion and system-overhead bytes for the page;
a direct-memory access (DMA) controller for accessing the flash-memory chips by generating commands to the flash-memory chips;
a volatile cache memory for storing pages of data transferred from the flash-memory chips by the DMA controller, the volatile cache memory organized to store the system-overhead bytes for a page with the data portion of the page;
a host interface for receiving commands from a host and for transferring data to the host from the flash-memory system; and
an overhead-byte generator, coupled to the host interface, for appending dummy overhead bytes to each page of data from the host, the dummy overhead bytes written to the volatile cache memory as the system-overhead bytes when the data portion of the page is transferred from the host to the volatile cache memory, the overhead-byte generator including stripping means for removing the system-overhead bytes from the page when the page is transferred from the volatile cache memory to the host interface for reading by the host,whereby the system-overhead bytes are stored in the volatile cache memory and in the flash-memory chips but not transferred to or from the host.
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Accused Products
Abstract
A flash-memory system adds system-overhead bytes to each page of data stored in flash memory chips. The overhead bytes store system information such as address pointers for bad-block replacement and write counters used for wear-leveling. The overhead bytes also contain an error-correction (ECC) code when stored in the flash-memory chips. A DRAM cache stores the pages of data as enlarged pages with the overhead bytes, even though the enlarged pages are not aligned to a power of 2. When an enlarged page is read out of a flash-memory chip, its ECC code is immediately checked and the ECC code in the overhead bytes is replaced with a syndrome code and stored in the DRAM cache. A local processor for the flash-memory system then reads the syndrome code in the overhead bytes and repairs any error using repair information in the syndrome. The overhead bytes are stripped off when pages are transferred from the DRAM cache to a host. The host can be notified early by an intermediate interrupt after a programmable number of pages have been read. This improves performance since the host does not have to wait for an entire block of pages to be read.
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Citations
20 Claims
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1. A flash-memory system that transparently manages system-overhead bytes, the flash-memory system comprising:
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a plurality of non-volatile flash-memory chips, each flash-memory chip storing a plurality of blocks of pages, each page having a data portion and system-overhead bytes for the page; a direct-memory access (DMA) controller for accessing the flash-memory chips by generating commands to the flash-memory chips; a volatile cache memory for storing pages of data transferred from the flash-memory chips by the DMA controller, the volatile cache memory organized to store the system-overhead bytes for a page with the data portion of the page; a host interface for receiving commands from a host and for transferring data to the host from the flash-memory system; and an overhead-byte generator, coupled to the host interface, for appending dummy overhead bytes to each page of data from the host, the dummy overhead bytes written to the volatile cache memory as the system-overhead bytes when the data portion of the page is transferred from the host to the volatile cache memory, the overhead-byte generator including stripping means for removing the system-overhead bytes from the page when the page is transferred from the volatile cache memory to the host interface for reading by the host, whereby the system-overhead bytes are stored in the volatile cache memory and in the flash-memory chips but not transferred to or from the host. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A flash-memory storage peripheral comprising:
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a host interface for transferring host pages to and from a host, the host pages having only a data portion; a local processor for controlling the flash-memory storage peripheral; a read-only memory (ROM), coupled to the local processor, for storing routines for execution by the local processor, the routines including wear-leveling routines for re-mapping data from over-used or faulty memory blocks to under-used or unused memory blocks; a cache, coupled to the local processor, for temporarily storing data from the host; each page stored in the cache having the data portion and an overhead portion, the overhead portion storing wear-leveling information and syndrome code for flash memory; a plurality of flash-memory chips, arranged into banks, the flash-memory chips being non-volatile semiconductor memory chips that retain data when power is lost, the flash-memory chips including a first flash-memory chip; a first flash-specific DMA controller, coupled to the local processor, for generating command, address, and data sequences to the first flash-memory chip in a format required by the first flash-memory chip; a first flash bus, coupled to the first flash-specific DMA controller, for transferring data, address, and commands over shared address/data/command lines; one or more flash buffer chips, coupled to the first flash bus, for transporting the data, address, and commands between the shared lines of the first flash bus and the flash-memory chips; wherein the flash-memory chips store blocks of pages, each page having the data portion and the overhead portion, the overhead portion storing wear-leveling information and error-correction code for the page stored in the flash-memory chips, whereby the overhead portion of the page is stored in the flash-memory chips and in the cache, but the overhead portion is not transferred to and from the host. - View Dependent Claims (17, 18)
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19. A method of reading data from a non-volatile flash-memory system to a host comprising the steps of:
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receiving a request from the host for reading a requested page of flash memory; generating in a local processor a block-read command to a direct-memory access (DMA) controller for a block containing the requested page; generating from the DMA controller a sequence of page-read commands to flash-memory chips; reading a page from a flash-memory chip in response to de-activation of a busy signal from the flash-memory chip for each page-read command; checking for errors in a data portion of the page from the flash-memory chip by processing the data portion with error-correction code in overhead bytes stored with the page in the flash-memory chip to produce a syndrome code; over-writing the error-correction code in the overhead bytes with the syndrome code, the syndrome code indicating when an error is detected in the data portion of the page; storing in a volatile cache memory the data portion and the overhead bytes with the syndrome code for each page read from the flash-memory chips; transferring the data portion but not the overhead bytes to the host from the volatile cache memory; and signaling the local processor after the requested page has been read to the volatile cache memory but before all pages in the block have been read from the flash-memory chips. - View Dependent Claims (20)
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Specification