Transparent management at host interface of flash-memory overhead-bytes using flash-specific DMA having programmable processor-interrupt of high-level operations

• US 5,956,743 A
• Filed: 09/29/1997
• Issued: 09/21/1999
• Est. Priority Date: 08/25/1997
• Status: Expired due to Term

• Current Assignee: BiTMICRO, LLC (BiTMICRO Networks, Inc.)
• Original Assignee: Bit Microsystems, Inc.
• Inventors: Bruce, Ricardo H., Bruce, Rolando H., Cohen, Earl T.
• Primary Examiner(s): Chan, Eddie P.
• Assistant Examiner(s): Portka, Gary J.
• Application Number:
  US08/939,602
• Time in Patent Office: 722 Days
• Field of Search: 711/103, 711/156, 714/5, 714/6, 714/8, 714/42, 714/52, 714/54, 714/758, 714/763, 714/766, 714/773, 714/764, 714/785, 714/770
• US Class Current: 711/103
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 2212/1036 Life time enhancement
• CPC Class Codes: G06F 2212/7211 Wear leveling

Abstract

A flash-memory system adds system-overhead bytes to each page of data stored in flash memory chips. The overhead bytes store system information such as address pointers for bad-block replacement and write counters used for wear-leveling. The overhead bytes also contain an error-correction (ECC) code when stored in the flash-memory chips. A DRAM cache stores the pages of data as enlarged pages with the overhead bytes, even though the enlarged pages are not aligned to a power of 2. When an enlarged page is read out of a flash-memory chip, its ECC code is immediately checked and the ECC code in the overhead bytes is replaced with a syndrome code and stored in the DRAM cache. A local processor for the flash-memory system then reads the syndrome code in the overhead bytes and repairs any error using repair information in the syndrome. The overhead bytes are stripped off when pages are transferred from the DRAM cache to a host. The host can be notified early by an intermediate interrupt after a programmable number of pages have been read. This improves performance since the host does not have to wait for an entire block of pages to be read.

Claims

1. A flash-memory system that transparently manages system-overhead bytes, the flash-memory system comprising:

a plurality of non-volatile flash-memory chips, each flash-memory chip storing a plurality of blocks of pages, each page having a data portion and system-overhead bytes for the page;

a direct-memory access (DMA) controller for accessing the flash-memory chips by generating commands to the flash-memory chips;

a volatile cache memory for storing pages of data transferred from the flash-memory chips by the DMA controller, the volatile cache memory organized to store the system-overhead bytes for a page with the data portion of the page;

a host interface for receiving commands from a host and for transferring data to the host from the flash-memory system; and

an overhead-byte generator, coupled to the host interface, for appending dummy overhead bytes to each page of data from the host, the dummy overhead bytes written to the volatile cache memory as the system-overhead bytes when the data portion of the page is transferred from the host to the volatile cache memory, the overhead-byte generator including stripping means for removing the system-overhead bytes from the page when the page is transferred from the volatile cache memory to the host interface for reading by the host,

whereby the system-overhead bytes are stored in the volatile cache memory and in the flash-memory chips but not transferred to or from the host.

2. The flash-memory system of claim 1 wherein the system-overhead bytes comprise:

a system field; and

an error-correction code (ECC) field for storing ECC for the data portion of the page.

3. The flash-memory system of claim 2 wherein the system field is located immediately after the data portion of the page, and the ECC stored in the ECC field includes error correction for the data portion and for the system field.

4. The flash-memory system of claim 2 wherein the system fields from each page in a block of pages are combined into a system-block field, the system-block field comprising system information for all pages in the block,

whereby system fields from pages in the block are combined to store the system information for the block of pages, but the ECC field for each page stores ECC for the page.

5. The flash-memory system of claim 4 wherein the system information stored in the system-block field comprises:

a write count for indicating a number of writes to a physical block of pages in the flash-memory chips; and

an address field for storing an address for the block.

6. The flash-memory system of claim 5 wherein the address field stores a logical-block address (LBA) for the block, the logical-block address being a portion of a logical address used by the host to address the block rather than a physical address of the block used to access the flash-memory chips,

whereby the system-overhead bytes store the portion of the logical address rather than a physical address for the block.

7. The flash-memory system of claim 6 wherein the system field of each page is one byte while the ECC field for a page is 15 bytes.

8. The flash-memory system of claim 1 wherein the data portion of the page has a total number of bytes equal to an integer power of 2, while an expanded page including the data portion and the system-overhead bytes has a total number of bytes that is not equal to an integer power of 2, wherein the expanded page is not aligned to powers of 2.

9. The flash-memory system of claim 1 wherein the DMA controller further comprises:

an error-correction code (ECC) checker, receiving the data portion and the system-overhead bytes from the flash-memory chips, for detecting errors in the data portion read from a page in the flash-memory chips;

a syndrome generator, in the ECC checker, for generating a syndrome code indicating whether any error is detected, and for indicating a location of an error within the page when an error is detected; and

over-writing means, coupled to the syndrome generator, for overwriting the ECC field in the system-overhead bytes with the syndrome code.

10. The flash-memory system of claim 9 wherein the volatile cache memory stores the syndrome code while the flash-memory chips store the error-correction code (ECC) in the system-overhead bytes for the page.

11. The flash-memory system of claim 10 wherein the DMA controller further comprises:

an ECC generator, receiving the data portion from the volatile cache memory, for generating error-correction code in the ECC field for the data portion of the page when the page is transferred from the volatile cache memory to the flash-memory chips.

12. The flash-memory system of claim 11 further comprising:

a local processor for the flash-memory system, coupled to the volatile cache memory and coupled to the host interface, for controlling the pages stored in the volatile cache memory and for responding to requests from the host.

13. The flash-memory system of claim 12 wherein the local processor includes:

repair means for repairing the error in the data portion of the page using the syndrome code stored in the system-overhead bytes.

14. The flash-memory system of claim 13 wherein the local processor includes a means for generating a single block-read command to the DMA controller, and

wherein the DMA controller includes sequencing means for generating a sequence of page-read commands to the flash-memory chips in response to the single block-read command from the local processor.

15. The flash-memory system of claim 14 further comprising:

intermediate interrupt means, responsive to the DMA controller, for generating an interrupt to the local processor after some but not all pages in a block have been read from the flash-memory chips to the volatile cache memory.

16. A flash-memory storage peripheral comprising:

a host interface for transferring host pages to and from a host, the host pages having only a data portion;

a local processor for controlling the flash-memory storage peripheral;

a read-only memory (ROM), coupled to the local processor, for storing routines for execution by the local processor, the routines including wear-leveling routines for re-mapping data from over-used or faulty memory blocks to under-used or unused memory blocks;

a cache, coupled to the local processor, for temporarily storing data from the host;

each page stored in the cache having the data portion and an overhead portion, the overhead portion storing wear-leveling information and syndrome code for flash memory;

a plurality of flash-memory chips, arranged into banks, the flash-memory chips being non-volatile semiconductor memory chips that retain data when power is lost, the flash-memory chips including a first flash-memory chip;

a first flash-specific DMA controller, coupled to the local processor, for generating command, address, and data sequences to the first flash-memory chip in a format required by the first flash-memory chip;

a first flash bus, coupled to the first flash-specific DMA controller, for transferring data, address, and commands over shared address/data/command lines;

one or more flash buffer chips, coupled to the first flash bus, for transporting the data, address, and commands between the shared lines of the first flash bus and the flash-memory chips;

wherein the flash-memory chips store blocks of pages, each page having the data portion and the overhead portion, the overhead portion storing wear-leveling information and error-correction code for the page stored in the flash-memory chips,

whereby the overhead portion of the page is stored in the flash-memory chips and in the cache, but the overhead portion is not transferred to and from the host.

17. The flash-memory storage peripheral of claim 16 wherein the overhead portion and the data portion of the page are read together by a single command to the flash-memory chips.

18. The flash-memory storage peripheral of claim 17 further comprising:

a second flash-specific DMA controller, coupled to the local processor, for generating command, address, and data sequences to a second flash-memory chip in a format required by the second flash-memory chip;

a second flash bus, coupled to the second flash-specific DMA controller, for transferring the data, address, and commands over shared address/data/command lines;

one or more flash buffer chips, coupled to the second flash bus, for transporting the data, address, and commands between the shared lines of the second flash bus and the second flash-memory chip;

whereby two flash-specific DMA controllers control access of flash-memory chips through flash buffer chips connected by two flash buses.

19. A method of reading data from a non-volatile flash-memory system to a host comprising the steps of:

receiving a request from the host for reading a requested page of flash memory;

generating in a local processor a block-read command to a direct-memory access (DMA) controller for a block containing the requested page;

generating from the DMA controller a sequence of page-read commands to flash-memory chips;

reading a page from a flash-memory chip in response to de-activation of a busy signal from the flash-memory chip for each page-read command;

checking for errors in a data portion of the page from the flash-memory chip by processing the data portion with error-correction code in overhead bytes stored with the page in the flash-memory chip to produce a syndrome code;

over-writing the error-correction code in the overhead bytes with the syndrome code, the syndrome code indicating when an error is detected in the data portion of the page;

storing in a volatile cache memory the data portion and the overhead bytes with the syndrome code for each page read from the flash-memory chips;

transferring the data portion but not the overhead bytes to the host from the volatile cache memory; and

signaling the local processor after the requested page has been read to the volatile cache memory but before all pages in the block have been read from the flash-memory chips.

20. The method of claim 19 further comprising repairing an error in the data portion of a page by:

reading the syndrome code in the overhead bytes for the page;

using location information in the syndrome code to locate the error in the data portion of the page; and

correcting the error using a processor that reads the location information in the syndrome code.