Multiprocessing system configured to perform synchronization operations

• US 5,958,019 A
• Filed: 07/01/1996
• Issued: 09/28/1999
• Est. Priority Date: 07/01/1996
• Status: Expired due to Term

• Current Assignee: Oracle America, Inc. (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Hagersten, Erik E., Nguyen, Hien, Yang, Shaw-Wen, Guzovskiy, Aleksandr, Zak, Robert C. Jr., Wong-Chan, Monica C., Nesheim, William A.
• Primary Examiner(s): Dinh, Dung C.
• Application Number:
  US08/674,328
• Time in Patent Office: 1,184 Days
• Field of Search: 395/200.43, 395/200.31, 395/200.32, 395/553, 395/800.13, 711/144, 711/145, 711/146, 711/141
• US Class Current: 713/375
• CPC Class Codes: G06F 12/0828 with concurrent directory accessing, i.e. handling multiple concurrent coherency transactions
• CPC Class Codes: G06F 9/52 Program synchronisation; Mutual exclusion, e.g. by means of semaphores

Abstract

When a processor within a computer system performs a synchronization operation, the system interface within the node delays subsequent transactions from the processor until outstanding coherency activity is completed. Therefore, the computer system may employ asynchronous operations. The synchronization operations may be used when needed to guarantee global completion of one or more prior asynchronous operations. In one embodiment, the synchronization operation is placed into a queue within the system interface. When the synchronization operation reaches the head of the queue, it may be initiated within the system interface. The system interface further includes a request agent comprising multiple control units, each of which may concurrently service coherency activity with respect to a different transaction. Furthermore, the system interface includes a synchronization control vector register which stores a bit for each control unit. Upon initiation of the synchronization operation within the system interface, bits corresponding to those control units which are performing coherency activity (i.e. those which are not idle) are set while other bits are cleared. As each control unit returns to the idle state, the corresponding bit is cleared as well. Once all the bits within the synchronization control vector register are cleared, the coherency activity which was outstanding when the synchronization operation was initiated is complete. The synchronization operation may then be completed.

Claims

1. A processing node comprising:

a processor configured to perform a synchronization command; and

a request agent coupled to receive said synchronization command from said processor, wherein said request agent is configured to perform a synchronization operation upon receipt of said synchronization command, wherein said request agent comprises a plurality of control units, and wherein each of said plurality of control units is configured to initiate coherency activity with respect to a transaction, and wherein said plurality of control units are configured to operate upon different transactions in parallel.

2. The processing node as recited in claim 1 wherein said synchronization command comprises a write operation to a predefined address.

3. The processing node as recited in claim 1 wherein each of said plurality of control units are configured to convey a coherency request and to receive one or more coherency replies with respect to said transaction.

4. The processing node as recited in claim 1 wherein said request agent performs said synchronization by determining that each of said plurality of control units has entered an idle state at least once subsequent to receipt of said write transaction.

5. The processing node as recited in claim 4 wherein said request agent further comprises a synchronization control vector register, wherein said synchronization control vector register includes a bit corresponding to one of said plurality of control units, and wherein said bit is set upon receipt of said write transaction if said one of said plurality of control units is performing coherency activity.

6. The processing node as recited in claim 5 wherein said one of said plurality of control units is configured to indicate that said one of said plurality of control units is entering said idle state, and wherein said bit is cleared upon indication by said one of said plurality of control units that said one of said plurality of control units is entering said idle state.

7. The processing node as recited in claim 1 wherein said request agent further comprises a queue, wherein said request agent is configured to initiate said synchronization upon arrival of said write transaction at a head of said queue.

8. The processing node as recited in claim 7 further comprising a second control unit configured to reissue said write transaction upon completion of said synchronization.

9. The processing node as recited in claim 7 wherein said queue comprises a first transaction queue for storing coherent transactions and a second transaction queue for storing input/output transactions.

10. The processing node as recited in claim 9 wherein said synchronization is performed for coherent transactions if said specific predefined address comprises a first specific predefined address, and wherein said write operation is inserted into said first transaction queue upon receipt from said processor.

11. The processing node as recited in claim 10 wherein said synchronization is performed for input/output transactions if said specific predefined address comprises a second specific predefined address, and wherein said write operation is inserted into said second transaction queue upon receipt from said processor.

12. A computer system comprising:

a first processing node including a request agent and at least one processor, wherein said request agent is configured to perform coherency requests in response to transactions performed by said processor; and

a second processing node including a slave agent configured to perform coherency replies in response to said coherency requests;

wherein said request agent is configured to inhibit additional coherency requests in response to transactions performed by said processor until said coherency replies are received for coherency requests outstanding from said request agent upon receipt of a synchronization operation performed within said first processing node.

13. A method for performing synchronization comprising:

executing a synchronization operation in a processor within a processing node;

receiving said synchronization operation in a request agent within said processing node;

waiting for coherency activity initiated by said request agent prior to said receiving to complete; and

reissuing said synchronization operation within said processing node, whereby said synchronization operation is completed.

14. The method as recited in claim 13 wherein said synchronization operation comprises a write transaction having a specific predefined address.

15. The method as recited in claim 14 wherein said write transaction comprises a write stream transaction.

16. The method as recited in claim 13 wherein said request agent comprises a synchronization control vector register having a bit corresponding to one a plurality of control units within said request agent which are configured to concurrently initiate coherency activity.

17. The method as recited in claim 16 wherein said waiting comprises clearing said bit when said one of said plurality of control units enters an idle state.

18. The method as recited in claim 16 wherein said request agent further comprises a queue.

19. The method as recited in claim 18 wherein said waiting is initiated upon arrival of said synchronization operation at a head of said queue.

20. A method for synchronizing comprising:

executing at least one asynchronous operation;

executing a system level synchronizing operation subsequent to said asynchronous operation; and

executing a processor level synchronization operation subsequent to said system level synchronization operation.