System having a receive data register for storing at least nine data bits of frame and status bits indicating the status of asynchronous serial receiver

• US 5,958,024 A
• Filed: 08/29/1997
• Issued: 09/28/1999
• Est. Priority Date: 08/29/1997
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Typaldos, Melanie D., Maupin, Patrick E.
• Primary Examiner(s): Lee, Thomas C.
• Assistant Examiner(s): Park, Ilwoo
• Application Number:
  US08/920,930
• Time in Patent Office: 760 Days
• Field of Search: 324/312, 364/133, 370/438, 370/535, 375/220, 395/850, 395/250, 395/286, 395/309, 395/500, 395/566, 709/221, 709/234, 711/156, 710/9, 710/14, 710/26, 710/30
• US Class Current: 710/26
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices

Abstract

An asynchronous serial port having a control register and at least one data register exchanges data with a serial bus. The asynchronous serial port includes an indicator representing whether the data register contains all of the data bits, or whether some of the data may be stored in the control register. When a nine-bit data source (or any data source having more than eight bits of data) is received, the bits need not be divided among multiple registers, but can all be stored in the receive-data register. This is particularly useful during DMA or when the exchange of data has been suspended, for example by an interrupt, while additional frames may be received by the asynchronous serial port. Because frames are stored in a single register when an extended write bit or an extended read bit is set. Further, the receive data register also stores status bits associated with received data. This is especially useful during DMA operations, when status, including parity, frame, or overrun errors can be associated with a particular data item examining the stored DMA data itself.

Claims

1. An asynchronous serial port, comprising:

an asynchronous serial receiver configurable for receiving a frame over a serial bus, the frame having at least 9 data bits; and

a plurality of registers including a receive data register for storing the at least 9 data bits of the frame, wherein the receive data register further stores status bits indicating the status of the asynchronous serial receiver corresponding to the at least 9 data bits.

2. The asynchronous serial port of claim 1 further comprising:

an asynchronous serial transmitter for transmitting a second frame over the serial bus, the second frame having at least 9 data bits; and

the plurality of registers further including a transmit data register for holding the at least 9 data bits of the second frame.

3. The asynchronous serial port of claim 2, wherein the transmit data register is 16 bits wide.

4. The asynchronous serial port of claim 2, wherein the plurality of registers includes a control register with an extended write enable bit that when true enables the transmit data register to hold and transmit the at least 9 data bits, and when false restricts the transmit data register to hold 8 or less of the at least 9 data bits.

5. The asynchronous serial port of claim 1, further comprising a control register, the control register configurable to store none of the at least 9 data bits.

6. The asynchronous serial port of claim 1, wherein the receive data register is 16 bits wide.

7. The asynchronous serial port of claim 1, wherein the status bits include status for overrun, frame error, and parity error.

8. The asynchronous serial port of claim 7, wherein the plurality of registers includes a control register with an extended read enable bit that when true enables the receive data register to hold the at least 9 data bits and the status bits, and when false restricts the receive data register to hold 8 or less of the at least 9 data bits and no status bits.

9. An asynchronous serial port, comprising:

an asynchronous serial receiver configurable for receiving a frame over a serial bus, the frame having a plurality of data bits; and

a plurality of registers including a receive data register for storing both the plurality of data bits and status bits indicating the status of the asynchronous serial receiver corresponding to the received frame.

10. The asynchronous serial port of claim 9, wherein the status bits include status for overrun, frame error, and parity error.

11. The asynchronous serial port of claim 10, wherein the plurality of registers includes a control register with an extended read enable bit that when true enables the receive data register to hold the plurality of data bits and the status bits.

12. A microcontroller implemented as a single monolithic integrated circuit, comprising:

an execution unit for executing instructions; and

an asynchronous serial port comprising;

an asynchronous serial receiver configurable for receiving a frame over a serial bus, the frame having a plurality of data bits; and

a plurality of registers including a receive data register for holding the plurality of data bits and status bits indicating the status of the asynchronous serial receiver corresponding to the frame, the receive data register readable by a single read operation.

13. The microcontroller of claim 12, wherein the status bit includes status for overrun, frame error, and parity error.

14. The microcontroller of claim 13, further comprising:

a direct memory access (DMA) unit for transferring data to or from memory, the DMA unit coupled to and programmable by the execution unit,

wherein the DMA unit is configurable to read a plurality of data items corresponding to a plurality of received frames from the receive data register, each of the plurality of data items including a plurality of data bits and status bits reflecting the status of a corresponding received frame, and wherein the stored plurality of data items can include status bits indicating error in a corresponding received frame while indicating the associated data item to which the error applies.

15. The microcontroller of claim 12, further comprising:

a direct memory access (DMA) unit for transferring data to or from memory, the DMA unit coupled to and programmable by the execution unit,

wherein the DMA unit is configurable to read a plurality of data items corresponding to a plurality of received frames from the receive data register and store the plurality of data items in a memory, wherein the stored plurality of data items each include a plurality of data bits and status bits associated with the frame in which the plurality of data bits were received.

16. The microcontroller of claim 15, wherein the DMA unit is configurable to read the plurality of data items and store the data items in memory using word wide transfers.

17. A microcontroller implemented as a single monolithic integrated circuit, comprising:

an execution unit for executing instructions; and

an asynchronous serial port comprising;

an asynchronous serial receiver configurable for receiving a frame over a serial bus, the frame having at least 9 data bits; and

a plurality of registers including a receive data register for holding the at least 9 data bits and status bits indicating the status of the asynchronous serial receiver corresponding to the frame, the receive data register readable by a single read operation.

18. The microcontroller of claim 17, further comprising:

a direct memory access (DMA) unit for transferring data to or from memory, the DMA unit coupled to and programmable by the execution unit,

wherein the DMA unit is configurable to read a plurality of data items corresponding to a plurality of received frames from the receive data register and store the plurality of data items in a memory, wherein the stored plurality of data items each include a plurality of data bits and status bits associated with the frame on which the plurality of data bits were received.

19. The microcontroller of claim 18, wherein the DMA unit is configurable to read the plurality of data items and store the data items in memory using word wide transfers.

20. A method of receiving high speed asynchronous data in a microcontroller that includes a DMA unit, an asynchronous serial port, and an execution unit, the method comprising the steps of:

receiving a frame of asynchronous serial data by the asynchronous serial port;

determining status conditions indicating the status of the

asynchronous serial port corresponding to the received frame;

performing a DMA transfer by the DMA unit receiving a receive data register containing the data bits of the received frame and status bits corresponding to the status conditions from the asynchronous serial port; and

storing the read data item in a memory.

21. The method of claim 20, wherein the steps of claim 21 are repeated for a plurality of data items.

22. The method of claim 21, further comprising the step of:

reading an asynchronous serial port status register after repeating the steps of claim 21 to determine if any of the received frames caused an error.

23. The method of claim 22, further comprising the step of:

if it is determined that any of the received frames caused an error, reading the data stored in memory to determine which received frames caused an error.

24. A microcontroller comprising:

means for receiving a frame of asynchronous serial data;

means for determining status conditions indicating the status of the receiving means corresponding to the received frame; and

means for transferring data bits and corresponding status bits reflecting the status condition from the means for receiving and the means for determining to a memory.