Host microprocessor with apparatus for temporarily holding target processor state

• US 5,958,061 A
• Filed: 07/24/1996
• Issued: 09/28/1999
• Est. Priority Date: 07/24/1996
• Status: Expired due to Term

• Current Assignee: Hanger Solutions, LLC (IP Investments Group LLC)
• Original Assignee: Transmeta Corporation (Novafora, Inc.)
• Inventors: Wing, Malcolm John, Kelly, Edmund J.
• Primary Examiner(s): Palys, Joseph E.
• Application Number:
  US08/685,721
• Time in Patent Office: 1,161 Days
• Field of Search: 395/183.01, 395/183.04, 395/183.05, 395/183.09, 395/183.11, 395/183.13, 395/182.15, 395/182.13, 395/185.01, 395/185.1, 395/185.06 , 395/185.02, 395/385, 395/386, 395/591, 395/733, 395/182.3, 395/184.01, 395/561, 395/185.07
• US Class Current: 714/1
• CPC Class Codes: G06F 11/004 Error avoidance G06F11/07 and subgroups take precedence
• CPC Class Codes: G06F 9/3834 Maintaining memory consistency
• CPC Class Codes: G06F 9/3863 using multiple copies of the architectural state, e.g. shadow registers

Abstract

Apparatus for use in a processing system having a host processor capable of executing a first instruction set to assist in running instructions of a different instruction set which is translated to the first instruction set by the host processor including circuitry for temporarily storing memory stores generated until a determination that a sequence of translated instructions will execute without exception or error on the host processor, circuitry for permanently storing memory stores temporarily stored when a determination is made that a sequence of translated instructions will execute without exception or error on the host processor, and circuitry for eliminating memory stores temporarily stored when a determination is made that a sequence of translated instructions will generate an exception or error on the host processor.

Claims

1. A gated store buffer for controlling the execution of memory store operations to system memory generated during execution of a sequence of instructions by a processor comprising:

a plurality of storage positions,

means for transferring memory stores generated by the operation of a processor to the storage positions,

means for transferring memory stores in the storage positions to system memory when a sequence of instructions generating the stores is executed without generating an exception or an error, and

means for eliminating memory stores in the storage positions when execution of a sequence of instructions generating the stores generates an exception or an error.

2. A gated store buffer for controlling the execution of memory store operations to system memory generated during execution of a sequence of instructions by a processor comprising:

a plurality of storage positions,

means for transferring memory stores generated by the operation of a processor to the storage positions,

means for transferring memory stores in the storage positions to system memory when a sequence of instructions generating the stores is executed without generating an exception or an error comprising;

means for maintaining pointers to indicate a beginning and an end of memory stores generated by a sequence of instructions, and

means for moving a pointer from a first position designating the beginning of the memory stores in the buffer to a second position designating the end of the memory stores in the buffer, and

means for eliminating memory stores in the storage positions when execution of a sequence of instructions generating the stores generates an exception or an error.

3. A gated store buffer for controlling the execution of memory store operations to system memory generated during execution of a sequence of instructions by a processor comprising:

a plurality of storage positions,

means for transferring memory stores generated by the operation of a processor to the storage positions,

means for transferring memory stores in the storage positions to system memory when a sequence of instructions generating the stores is executed without generating an exception or an error, and

means for eliminating memory stores in the storage positions when execution of a sequence of instructions generating the stores generates an exception or an error including;

means for maintaining pointers to indicate a beginning and an end of memory stores generated by a sequence of instructions, and

means for changing a pointer from designating the end of the memory stores in the buffer to designating the beginning of the memory stores in the buffer.

4. A method of controlling the execution of memory store operations to system memory generated by execution of a sequence of instructions by a processor comprising:

transferring each memory store to a gated store buffer as it is generated,

writing all of the memory stores to system memory if the sequence of instructions does not generate an exception or error, and

eliminating all of the memory stores if the sequence of instructions generates an exception or error.

5. A method of controlling the execution of memory store operations to system memory generated by execution of a sequence of instructions by a processor comprising:

transferring each memory store to a gated store buffer as it is generated,

writing all of the memory stores to system memory if the sequence of instructions does not generate an exception or error including;

maintaining pointers indicating a beginning and an end of the memory stores generated by execution of the sequence of instructions,

using a value of a pointer designating the beginning of the memory stores in the buffer to designate the end of the memory stores in the buffer, and

eliminating all of the memory stores if the sequence of instructions generates an exception or error.

6. A method of controlling the execution of memory store operations to system memory generated by execution of a sequence of instructions by a processor comprising:

transferring each memory store to a gated store buffer as it is generated,

writing all of the memory stores to system memory if the sequence of instructions does not generate an exception or error, and

eliminating all of the memory stores if the sequence of instructions generates an exception or error, including;

maintaining pointers indicating a beginning and an end of the memory stores generated by execution of the sequence of instructions,

using a value of a pointer designating the end of the memory stores in the buffer to designate the beginning of the memory stores in the buffer.

7. A computer system comprising:

a microprocessor,

main memory,

means for controlling the execution of memory store operations generated by execution of instructions by the microprocessor comprising;

a gated store buffer for transferring memory stores generated by execution of a sequence of instructions by a processor comprising;

a plurality of storage positions;

means for transferring memory stores generated by the operation of a processor to the storage positions,

means for transferring memory stores in the storage positions to main memory when a sequence of instructions generating the stores is executed without generating an exception or an error, and

means for eliminating memory stores in the storage positions when execution of a sequence of instructions generating the stores generates an exception or an error.

8. A computer system comprising:

a microprocessor,

main memory,

means for controlling the execution of memory store operations generated by execution of instructions by the microprocessor comprising;

a gated store buffer for transferring memory stores generated by execution of a sequence of instructions by a processor comprising;

a plurality of storage positions;

means for transferring memory stores generated by the operation of a processor to the storage positions,

means for transferring memory stores in the storage positions to main memory when a sequence of instructions generating the stores is executed without generating an exception or an error, comprising;

means for maintaining pointers to indicate a beginning and an end of memory stores generated by a sequence of instructions, and

means for changing a pointer designating the beginning of the memory stores in the buffer to designating the end of the memory stores in the buffer, and

means for eliminating memory stores in the storage positions when execution of a sequence of instructions generating the stores generates an exception or an error.

9. A computer system comprising:

a microprocessor,

main memory,

means for controlling the execution of memory store operations generated by execution of instructions by the microprocessor comprising;

a gated store buffer for transferring memory stores generated by execution of a sequence of instructions by a processor comprising;

a plurality of storage positions;

means for transferring memory stores generated by the operation of a processor to the storage positions,

means for transferring memory stores in the storage positions to main memory when a sequence of instructions generating the stores is executed without generating an exception or an error, and

means for eliminating memory stores in the storage positions when execution of a sequence of instructions generating the stores generates an exception or an error, including;

means for maintaining pointers to indicate a beginning and an end of memory stores generated by a sequence of instructions, and

means for changing a pointer from designating the end of the memory stores in the buffer to designating the beginning of the memory stores in the buffer.

10. Apparatus for use in a processing system having a host processor capable of executing a first instruction set to assist in running instructions of a different instruction set which is translated to the first instruction set by the host processor comprising:

means for temporarily storing memory stores generated until a determination that a sequence of translated instructions will execute without exception or error on the host processor,

means for permanently storing memory stores temporarily stored when a determination is made that a sequence of translated instructions will execute without exception or error on the host processor, and

means for eliminating memory stores temporarily stored when a determination is made that a sequence of translated instructions will generate an exception or error on the host processor.

11. Apparatus as claimed in claim 10 in which the means for temporarily storing memory stores generated until a determination that a sequence of translated instructions will execute without exception or error on the host processor comprises:

a store buffer,

means for transferring memory stores to the store buffer, and

means for transferring memory stores from the store buffer to the means for permanently storing memory stores when a determination is made that a sequence of translated instructions will execute without exception or error on the host processor.

12. Apparatus as claimed in claim 10 in which the means for temporarily storing memory stores generated until a determination that a sequence of translated instructions will execute without exception or error on the host processor comprises:

an interim portion of memory,

means for transferring memory stores to the interim portion of memory, and

means for transferring memory stores from the interim portion of memory to overwrite the means for permanently storing memory stores when a determination is made that a sequence of translated instructions will execute without exception or error on the host processor.

13. Apparatus for use in a processing system having a host processor capable of executing a first instruction set to assist in running instructions of a different instruction set which is translated to the first instruction set by the host processor comprising:

means for temporarily storing memory stores generated until a determination that a sequence of translated instructions will execute without exception or error on the host processor, comprising;

means for transferring memory stores to the means for permanently storing memory stores, and

means for storing memory data replaced by the memory stores,

means for permanently storing memory stores temporarily stored when a determination is made that a sequence of translated instructions will execute without exception or error on the host processor, comprising;

means for eliminating memory data replaced by the memory stores if a sequence of translated instruction executes without exception or error on the host processor, and

means for eliminating memory stores temporarily stored when a determination is made that a sequence of translated instructions will generate an exception or error on the host processor, comprising;

means for replacing the memory stores in memory with the memory data replaced by the memory stores if a sequence of translated instructions generates an exception or error on the host processor.

14. Apparatus for use in a processing system comprising:

a host processor capable of executing a first instruction set to assist in running instructions of a different instruction set which is translated to the first instruction set by the host processor,

means for temporarily storing memory stores generated until a determination that a sequence of translated instructions will execute without exception or error on the host processor,

means for permanently storing memory stores temporarily stored when a determination is made that a sequence of translated instructions will execute without exception or error on the host processor, and

means for eliminating memory stores temporarily stored when a determination is made that a sequence of translated instructions will generate an exception or error on the host processor.

15. Apparatus as claimed in claim 14 in which the means for temporarily storing memory stores generated until a determination that a sequence of translated instructions will execute without exception or error on the host processor comprises:

a store buffer,

means for controlling the execution of memory store operations to the store buffer,

means for transferring memory stores from the store buffer to the means for permanently storing memory stores when a determination is made that a sequence of translated instructions will execute without exception or error on the host processor, and

means for eliminating memory stores in the store buffer when a determination is made that a sequence of translated instructions will generate an exception or error on the host processor.

16. Apparatus as claimed in claim 14 in which the means for temporarily storing memory stores generated until a determination that a sequence of translated instructions will execute without exception or error on the host processor comprises:

an interim portion of memory,

means for transferring memory stores to the interim portion of memory, and

means for transferring memory stores from the interim portion of memory to overwrite the means for permanently storing memory stores when a determination is made that a sequence of translated instructions will execute without exception or error on the host processor.

17. Apparatus for use in a processing system comprising:

a host processor capable of executing a first instruction set to assist in running instructions of a different instruction set which is translated to the first instruction set by the host processor,

means for temporarily storing memory stores generated until a determination that a sequence of translated instructions will execute without exception or error on the host processor, comprising;

means for transferring memory stores to memory, and

means for storing memory data replaced by the memory stores,

means for permanently storing memory stores temporarily stored when a determination is made that a sequence of translated instructions will execute without exception or error on the host processor, comprising;

means for dumping memory data replaced by the memory stores if a sequence of translated instruction executes without exception or error on the host processor, and

means for eliminating memory stores temporarily stored when a determination is made that a sequence of translated instructions will generate an exception or error on the host processor, comprising;

means for replacing the memory stores in memory with the memory data replaced by the memory stores if a sequence of translated instructions generates an exception or error on the host processor.

18. Apparatus for use in a processing system comprising:

a host processor capable of executing a first instruction set to assist in running instructions of a different instruction set which is translated to the first instruction set by the host processor,

the host processor comprising;

a processing unit including a set of target registers for storing state information which a target computer executing a program having the first instruction set would generate,

a set of working registers for storing state information which the host processor generates, the host processor responding to completion of the execution of a sequence of translated instructions without an exception or error to transfer values stored in working registers to target registers, and

the host processor responds to generation of an exception or error during of the execution of a sequence of translated instructions to transfer values stored in target registers to working registers,

means for temporarily storing memory stores generated until a determination that a sequence of translated instructions will execute without exception or error on the host processor,

means for permanently storing memory stores temporarily stored when a determination is made that a sequence of translated instructions will execute without exception or error on the host processor, and

means for eliminating memory stores temporarily stored when a determination is made that a sequence of translated instructions will generate an exception or error on the host processor.

19. A host processor capable of executing a first instruction set to assist in running instructions of a different instruction set which is translated to the first instruction set by the host processor,

the host processor comprising:

means for temporarily storing memory stores generated until a determination that a sequence of translated instructions will or will not execute without exception or error on the host processor;

means for temporarily holding last valid register states for a target processor generated while executing the sequence of translated instructions until a determination that the sequence of translated instructions will or will not execute without exception or error on the host processor, and

means for holding working state of the host processor generated while executing the sequence of translated instructions until a determination that the sequence of translated instructions will or will not execute without exception or error on the host processor.

20. A host processor as claimed in claim 19 in which the means for temporarily storing memory stores comprises a gated store buffer.

21. A host processor as claimed in claim 19 in which the means for temporarily holding last valid register states for a target processor comprises a set of official target registers, and

in which the means for holding working state of the host processor comprises a set of working registers.

22. A host processor as claimed in claim 19 in which the means for temporarily storing memory stores comprises a gated store buffer,

in which the means for temporarily holding last valid register states for a target processor comprises a set of official target registers, and

in which the means for holding working state of the host processor comprises a set of working registers.