Semiconductor device including an improved terminal structure

• US 5,959,324 A
• Filed: 07/11/1997
• Issued: 09/28/1999
• Est. Priority Date: 03/30/1992
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Kohyama, Yusuke
• Primary Examiner(s): LOKE, STEVEN HO YIN
• Application Number:
  US08/890,376
• Time in Patent Office: 809 Days
• Field of Search: 438/545, 438/548, 438/556, 438/561, 438/243, 438/244, 438/246, 438/247, 438/249, 438/386, 438/387, 438/389, 438/390, 438/392, 257/301, 257/296, 257/302, 257/303, 257/304, 257/305, 257/306
• US Class Current: 257/301
• CPC Class Codes: H10B 12/37 the capacitor being at least partially in a trench in the substrate

Abstract

A semiconductor device includes a first N-type region formed in a P-type silicon substrate, trenches formed in the substrate, second N-type regions each formed from at least the bottom of a corresponding one of the trenches into the substrate, these second N-type regions contacting each other to constitute a wiring layer and being also in contact with the first N-type region, and an electrode for applying a predetermined potential to the second N-type regions via the first N-type region. Since a potential is supplied to the wiring layer formed in the substrate via the first N-type region, no special design, such as formation of a terminal trench, is required. A potential can be easily supplied to the wiring layer formed in the semiconductor substrate, and the device can be easily fabricated.

Claims

1. A dynamic random access memory device comprising:

a semiconductor substrate of a first conductivity type;

a well region of a second conductivity type formed in said semiconductor substrate, said well region having a first width at a level which is located between a top and bottom thereof;

a plurality of trenches formed in said semiconductor substrate, said trenches being spaced apart from each other and a first trench of said trenches having an upper portion formed within a top surface of said well region;

semiconductor regions formed in said semiconductor substrate at bottom portions of said trenches, each semiconductor region having a second width less than the first width at a level which is located between a top and a bottom thereof and said semiconductor regions contacting each other to form a wiring layer;

capacitors formed in each of said plurality of trenches, each capacitor having a storage node insulated from said wiring layer;

switching transistors coupled to said capacitors formed in said trenches other than said first trench and at least a second trench adjacent to said first trench, each switching transistor comprising a gate electrode and a source/drain electrode coupled to the storage node of a respective corresponding one of said capacitors; and

a bit line coupled to a drain/source eletrode of each of said switching transistors.

2. The dynamic random access memory device according to claim 1, further comprising an electrode, electrically connected to said well region, for applying a potential to said wiring layer via said well region.

3. A dynamic random access memory device comprising:

s semiconductor substrate of a first conductivity type;

a well region of a second conductivity type formed in said semiconductor substrate, said well region having a first width at a level which is located between a top and bottom thereof;

a plurality of trenches formed in said semiconductor substrate, said trenches being spaced apart from each other and a first trench of said trenches having an upper portion formed within a top surface of said well region;

semiconductor regions formed in said semiconductor substrate at bottom portions of said trenches, each semiconductor region having a second width less than the first width at a level which is located between a top and a bottom thereof and said semiconductor regions contacting each other to form a wiring layer;

capacitors formed in each of said plurality of trenches, each capacitor having a storage node and an insulating film, said storage node being insulated from said wiring layer by the insulating film;

switching transistors coupled to said capacitors formed in said trenches other than said first trench and at least a second trench adjacent to said first trench, each switching transistor comprising a gate electrode and a source/drain electrode coupled to the storage node of a respective corresponding one of said capacitors; and

a bit line coupled to a drain/source electrode of each of said switching transistors.

4. A dynamic random access memory device comprising:

a semiconductor substrate of a first conductivity type;

a first well region of a second conductivity type formed in a major surface of said semiconductor substrate, said first well region having a first width between the two edges of said first well region and halfway between the top and bottom surfaces of said first well region;

a first trench having an upper portion located within the top surface of said first well region;

a plurality of second trenches formed in said major surface of said semiconductor substrate;

at least one third trench formed in said major surface of said semiconductor substrate, said third trench located between said first trench and said second trenches;

semiconductor regions formed at bottom portions of said first trench, said second trenches and said third trench respectively, and within said first well region and said semiconductor substrate, said semiconductor regions each having a second width between the two edges of one of said semiconductor regions and halfway between the top and bottom surfaces of said one of said semiconductor regions less than said first width, and said semiconductor regions contacting each other to form a wiring layer;

capacitors respectively formed in said first trench, said second trenches and said third trench, wherein each of said capacitors has a storage node insulated from said wiring layer;

cell transistors formed in said major surface of said semiconductor substrate, each cell transistor having a gate electrode and source/drain regions of the second conductivity type, wherein a first source/drain region of each of said cell transistors is respectively connected to the storage node of only those of said capacitors formed in said second trenches; and

a bit line electrically connected to a second source/drain region of each of said cell transistors.

5. The device according to claim 4, further comprising an electrode, electrically connected to said first well region, for applying a predetermined potential to said wiring layer via said first well region.

6. A dynamic random access memory device comprising:

a semiconductor substrate of a first conductivity type;

a well region of a second conductivity type formed in said semiconductor substrate, said well region having a first width at a level which is halfway between the top and bottom thereof;

a plurality of trenches formed in said semiconductor substrate, said trenches being spaced apart from each other and a first trench of said trenches having an upper portion formed within the top surface of said well region;

semiconductor regions formed in said semiconductor substrate at bottom portions of said trenches, each semiconductor region having a second width less than the first width at a level which is halfway between a top and a bottom thereof and said semiconductor regions contacting each other to form a wiring layer;

capacitors formed in each of said plurality of trenches, each capacitor comprising a storage node insulated from said wiring layer;

switching transistors coupled to said capacitors formed in said trenches other than said first trench and at least a second trench adjacent to said first trench, each switching transistor comprising a gate electrode and a source/drain electrode coupled to the storage node of a respective corresponding one of said capacitors; and

a bit line coupled to a drain/source electrode of each of said switching transistors.

7. The dynamic random access memory device according to claim 6, further comprising:

an electrode, electrically connected to said well region, for applying a potential to said wiring layer via said well region.

8. The dynamic random access memory device according to claim 6, wherein said capacitors comprise sheath capacitors.

9. A dynamic random access memory device comprising:

a semiconductor substrate of a first conductivity type;

a first well region of a second conductivity type formed in said semiconductor substrate, said first well region having a first width at a level which is halfway between the top and bottom thereof;

a second well region of the first conductivity type formed in said semiconductor substrate;

a third well region of the second conductivity type formed in said semiconductor substrate;

a fourth well region of the second conductivity type formed in said semiconductor substrate;

a fifth well region of the first conductivity type formed in said fourth well region;

a plurality of spaced apart trenches, a first of said trenches having an upper portion within the top surface of said first well region, and the remainder of said trenches formed to extend through said second well region;

semiconductor regions formed in said semiconductor substrate at bottom portions of said trenches, each semiconductor region having a second width less than the first width at a level which is halfway between the top and bottom thereof and said semiconductor regions contacting each other to form a wiring layer disposed below said second well region;

capacitors formed in said trenches, each capacitor comprising a storage node insulated from said wiring layer;

switching transistors coupled to said capacitors formed in said trenches other than said first trench and at least a second trench adjacent to said first trench, each switching transistor comprising a gate electrode and a source/drain electrode coupled to the storage node of a respective corresponding one of said capacitors;

a bit line coupled to a drain/source electrode of each of said switching transistors;

a first electrode, electrically connected to said first well region, for applying a first potential to said wiring layer via said first well region;

a second electrode, electrically connected to said second well region, for applying a second potential to said second well region;

a third electrode, electrically connected to said third well region, for applying a third potential to said third well region; and

a fourth electrode, electrically connected to said fifth well region, for applying a fourth potential to said fifth well region.

10. A dynamic random access memory device comprising:

a semiconductor substrate of a first conductivity type;

a first well region of a second conductivity type formed in a major surface of said semiconductor substrate, said first well region having a first width between two edges which are located between top and bottom surfaces of said first well region;

a first trench having an upper portion located within the top surface of said first well region;

a plurality of second trenches formed in said major surface of said semiconductor substrate;

at least one third trench formed in said major surface of said semiconductor substrate, said third trench located between said first trench and said second trenches;

semiconductor regions formed at bottom portions of said first trench, said second trenches and said third trench respectively, and within said first well region and said semiconductor substrate, said semiconductor regions each having a second width between two edges which are located between top and bottom surfaces of one of said semiconductor regions less than said first width, and said semiconductor regions contacting each other to form a wiring layer;

capacitors respectively formed in said first trench, said second trenches and said third trench, wherein each of said capacitors has a storage node insulated from said wiring layer;

cell transistors formed in said major surface of said semiconductor substrate, each cell transistor having a gate electrode and source/drain regions of the second conductivity type, wherein a first source/drain region of each of said cell transistors is respectively connected to the storage node of only those of said capacitors formed in said second trenches; and

a bit line electrically connected to a second source/drain region of each of said cell transistors.

11. The dynamic random access memory device according to claim 10 further comprising an electrode electrically connected to said first well region for applying a predetermined potential to said wiring layer via said first well region.

12. A dynamic random access memory device comprising:

a semiconductor substrate of a first conductivity type;

a first well region of a second conductivity type formed in said semiconductor substrate, said first well region having a first width at a level which is located between a top and bottom thereof;

a second well region of the first conductivity type formed in said semiconductor substrate;

a third well region of the second conductivity type formed in said semiconductor substrate;

a fourth well region of the second conductivity type formed in said semiconductor substrate;

a fifth well region of the first conductivity type formed in said fourth well region;

a plurality of spaced apart trenches, a first trench of said trenches having an upper portion within a top surface of said first well region, and the remainder of said trenches formed to extend through said second well region;

semiconductor regions formed in said semiconductor substrate at bottom portions of said trenches, each semiconductor region having a second width less than the first width at a level which is located between a top and bottom thereof and said semiconductor regions contacting each other to form a wiring layer disposed below said second well region;

capacitors formed in said trenches, each capacitor having a storage node insulated from said wiring layer;

switching transistors coupled to said capacitors formed in said trenches other than said first trench and at least a second trench adjacent to said first trench, each switching transistor comprising a gate electrode and a source/drain electrode coupled to the storage node of a respective corresponding one of said capacitors;

a bit line coupled to a drain/source electrode of each of said switching transistors;

a first electrode, electrically connected to said first well region, for applying a first potential to said wiring layer via said first well region;

a second electrode, electrically connected to said second well region, for applying a second potential to said second well region;

a third electrode, electrically connected to said third well region, for applying a third potential to said third well region; and

a fourth electrode, electrically connected to said fifth well region, for applying a fourth potential to said fifth well region.

13. A dynamic random access memory device comprising:

a semiconductor substrate of a first conductivity type;

a first well region of a second conductivity type formed in a major surface of said semiconductor substrate, said first well region having a first width between two edges which are located between top and bottom surfaces of said first well region;

a first trench having an upper portion located within the top surface of said first well region;

a plurality of second trenches formed in said major surface of said semiconductor substrate;

at least one third trench formed in said major surface of said semiconductor substrate, said third trench located between said first trench and said second trenches;

semiconductor regions formed at bottom portions of said first trench, said second trenches and said third trench respectively, and within said first well region and said semiconductor substrate, said semiconductor regions each having a second width between two edges which are located between top and bottom surfaces of one of said semiconductor regions less than said first width, and said semiconductor regions contacting each other to form a wiring layer;

capacitors respectively formed in said first trench, said second trenches and said third trench, wherein each of said capacitors has a storage node and an insulating film, said storage node being insulated from said wiring layer by the insulating film;

cell transistors formed in said major surface of said semiconductor substrate, each cell transistor having a gate electrode and source/drain regions of the second conductivity type, wherein a first source/drain region of each of said cell transistors is respectively connected to the storage node of only those of said capacitors formed in said second trenches; and

a bit line electrically connected to a second source/drain region of each of said cell transistors.

14. A dynamic random access memory device comprising:

a semiconductor substrate of a first conductivity type;

a first well region of a second conductivity type formed in said semiconductor substrate, said first well region having a first width at a level which is located between a top and bottom thereof;

a second well region of the first conductivity type formed in said semiconductor substrate;

a third well region of the second conductivity type formed in said semiconductor substrate;

a fourth well region of the second conductivity type formed in said semiconductor substrate;

a fifth well region of the first conductivity type formed in said fourth well region;

a plurality of spaced apart trenches, a first trench of said trenches having an upper portion within a top surface of said first well region, and the remainder of said trenches formed to extend through said second well region;

semiconductor regions formed in said semiconductor substrate at bottom portions of said trenches, each semiconductor region having a second width less than the first width at a level which is located between a top and bottom thereof and said semiconductor regions contacting each other to form a wiring layer disposed below said second well region;

capacitors formed in said trenches, each capacitor having a storage node and an insulating film, said storage node being insulated from said wiring layer by the insulating film;

switching transistors coupled to said capacitors formed in said trenches other than said first trench and at least a second trench adjacent to said first trench, each switching transistor comprising a gate electrode and a source/drain electrode coupled to the storage node of a respective corresponding one of said capacitors;

a bit line coupled to a drain/source electrode of each of said switching transistors;

a first electrode, electrically connected to said first well region, for applying a first potential to said wiring layer via said first well region;

a second electrode, electrically connected to said second well region, for applying a second potential to said second well region;

a third electrode, electrically connected to said third well region, for applying a third potential to said third well region; and

a fourth electrode, electrically connected to said fifth well region, for applying a fourth potential to said fifth well region.