Defect monitor and method for automated contactless inline wafer inspection

• US 5,959,459 A
• Filed: 12/10/1996
• Issued: 09/28/1999
• Est. Priority Date: 12/10/1996
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Kebede, Tessema, Satya, Akella Venkata Surya, Bentson, Leon Ray
• Primary Examiner(s): Ballato, Josie
• Assistant Examiner(s): KOBERT, RUSSELL MARC
• Application Number:
  US08/763,189
• Time in Patent Office: 1,022 Days
• Field of Search: 324/500, 324/501, 324/751, 250/310, 250/311
• US Class Current: 324/754.22
• CPC Class Codes: G01R 31/307 of integrated circuits

Abstract

According to the preferred embodiment, a defect monitor is provided that facilitates the location and characterization of defects in a semiconductor device. The defect monitors are designed to facilitate automated scanning electron microscope in voltage contrast mode (SEM-VC) inspection. The defect monitors include a plurality of flags used to quickly locate defects. The SEM-VC magnification can then be increased to further isolate and characterize the defects as necessary. Thus, the preferred embodiment facilitates the use of SEM-VC scanning procedures to automatically detect and locate faults at low magnification, and then characterize the faults a higher magnification, resulting in a much higher throughput.

Claims

1. A defect monitor for locating and characterizing the defects in a semiconductor device using a scanning electron microscope in voltage contrast mode (SEM-VC), the defect monitor comprising:

a) a plurality of floating monitor shapes, said plurality of monitor shapes comprising conducting material fabricated into a first level of said semiconductor device;

b) a plurality of monitor lines, said plurality of monitor lines fabricated into said first level of said semiconductor device, said plurality of monitor lines being interdigited between said plurality of floating monitor shapes, said plurality of monitor lines each grounded at a first end;

c) a plurality of flags, said flags comprising conducting material, each of said plurality of flags connected to a second end of said plurality of monitor lines, wherein any of said plurality of flags that are grounded through said plurality of monitor lines provide a contrast with said plurality of flags that are floating due to a defect when said plurality of flags are scanned by said SEM-VC.

2. The defect monitor of claim 1 wherein said each of said plurality of monitor shapes has an area between 10-50 μ

m².

3. The defect monitor of claim 1 wherein said each of said plurality of flags has an area between 10-50 μ

m².

4. The defect monitor of claim 1 wherein said plurality of flags are arranged in a column.

5. The defect monitor of claim 1 wherein said plurality of monitor shapes are arranged in a plurality of columns with adjacent columns offset.

6. The defect monitor of claim 1 wherein said plurality of monitor lines are fabricated a predetermined distance from said monitor shapes and wherein said predetermined distance is substantially equal to a minimum design width of said semiconductor device.

7. The defect monitor of claim 1 further comprising a plurality of interlevel monitor shapes, said interlevel monitor shapes fabricated to be floating in a second level above said monitor shapes and said monitor lines.

8. The defect monitor of claim 1 further wherein said plurality of flags are arranged in a column and wherein said plurality of monitor shapes are arranged in a array adjacent said column of flags, such that said SEM-VC scan of said plurality of flags scans down said column of flags and wherein said contrast indicates the presence of a defect and wherein said SEM-VC scan then scans down said array of monitor shapes until said defect is located.

9. A defect monitor for locating and characterizing the defects in a semiconductor device using a scanning electron microscope in voltage contrast mode (SEM-VC), the defect monitor comprising:

a) a plurality of floating monitor shapes, each of said plurality of floating monitor shapes comprising conducting material fabricated into a first level of said semiconductor device, said plurality of floating monitor shapes arranged in an array;

b) a plurality of monitor lines, said plurality of monitor lines fabricated into said first level of said semiconductor device, each of said plurality of monitor lines grounded at a first end, said plurality of monitor lines running between said plurality of monitor shapes and maintaining a distance to said plurality of monitor shapes substantially equal to a minimum conductor distance during at least a portion of their run;

c) a plurality of flags, said flags comprising conducting material, each of said plurality of flags connected to a second end of each of said plurality of monitor lines;

wherein said plurality of flags that are grounded through said plurality of monitor lines contrast with said plurality of flags that are floating when said plurality of flags are scanned by said SEM-VC and wherein said plurality of monitor shapes that are grounded due to a defect contrast with said plurality of monitor shapes that are floating.

10. A method for determining the distribution and character of defects in a semiconductor device, the method comprising the steps of:

a) providing a defect monitor, said defect monitor including;

i) a plurality of floating monitor shapes, said plurality of monitor shapes comprising conducting material fabricated into a first level of said semiconductor device;

ii) a plurality of monitor lines, said plurality of monitor lines fabricated into said first level of said semiconductor device, said plurality of monitor lines being interdigited between said plurality of floating monitor shapes;

said plurality of monitor lines each being grounded at a first end;

iii) a plurality of flags, said flags comprising conducting material, each of said plurality of flags connected to a second end of said plurality of monitor lines;

b) scanning said plurality of flags with a scanning electron microscope in voltage contrast mode (SEM-VC) such that any of said plurality of flags which are not grounded through said plurality of monitor lines due to a defect will contrast with said plurality of flags that are grounded through said plurality of monitor lines.

11. The method of claim 10 further comprising:

a) locating each of said plurality of flags that is ungrounded;

b) scanning said monitor lines connected to said ungrounded plurality of flags with a SEM-VC scan until defect causing said monitor line open is located.

12. The method of claim 10 further comprising:

a) scanning said plurality of monitor shapes with said SEM-VC; and

b) locating each of said plurality of monitor shapes which are grounded though said plurality of monitor lines.

13. The method of claim 10 further comprising:

a) providing a plurality of floating interlevel monitor shapes at a second level of said semiconductor device;

b) scanning said plurality of interlevel monitor shapes with a SEM-VC scan, such that each of said plurality of floating interlevel monitor shapes which are grounded are contrasted from said floating interlevel monitor shape.

14. The method of claim 10 wherein the step of scanning said plurality of flags comprises scanning at a magnification between 60×

and 100×

.

15. The method of claim 11 wherein the step of scanning said plurality of flags comprises scanning at a magnification between 60×

and 100× and

wherein the step of scanning said monitor lines connected to said ungrounded plurality of flags comprises scanning at a magnification between 500× and

1000×

.