Bus driver circuit including a slew rate indicator circuit having a one shot circuit

• US 5,959,481 A
• Filed: 02/18/1997
• Issued: 09/28/1999
• Est. Priority Date: 02/18/1997
• Status: Expired due to Term

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Garlepp, Bruno, Ching, Michael, Donnelly, Kevin S., Tran, Chanh
• Primary Examiner(s): Callahan, Timothy P.
• Assistant Examiner(s): KIM, JUNG H
• Application Number:
  US08/801,521
• Time in Patent Office: 952 Days
• Field of Search: 327/16, 327/20, 327/161, 327/170, 327/172, 327/175, 327/176, 327/227, 327/229, 327/269, 327/284, 327/285, 327/291, 326/32, 326/27, 326/87
• US Class Current: 327/170
• CPC Class Codes: G06F 13/4072 Drivers or receivers G06F13/4086 takes precedence; for multistate logic circuits H03K19/0002

Abstract

A bus driver circuit having slew rate control. According to one embodiment, the bus driver circuit includes the following elements: a first circuit having an input configured to receive a data signal and an output operative to output a drive signal in response to the data signal; a second circuit coupled in parallel with the first circuit and operative to receive a slew rate control signal; and a slew rate indicator circuit coupled to the second circuit. The slew rate indicator circuit determines the state of the slew rate control signal in response to operating conditions that cause variations in the slew rate of the drive signal such that when the slew rate control signal is asserted, the second circuit is enabled to affect the slew rate of the drive signal. For one embodiment, the slew rate indicator includes a pulse generator circuit and a clocked comparator circuit. The pulse generator circuit is operative to receive a clock signal and generate a pulse in response to a first transition of the clock signal. The clocked comparator is coupled to the pulse generator circuit and operative to receive the pulse. The clocked comparator determines the state of the slew rate control signal by sampling for the pulse in response to a second transition of the clock signal.

Claims

1. A driver circuit having a controlled slew rate, comprising:

a first circuit having an input coupled to receive a data signal and an output operative to output a drive signal in response to the data signal;

a second circuit coupled in parallel with the first circuit and operative to receive a slew rate control signal; and

a slew rate indicator circuit coupled to the second circuit, the slew rate indicator circuit determining the state of the slew rate control signal in response to operating conditions that cause variations in the slew rate of the drive signal such that when the slew rate control signal is asserted, then the second circuit is enabled to affect the slew rate of the drive signal, wherein the slew rate indicator circuit comprises;

a one-shot circuit operative to receive a clock signal, the one-shot circuit generating a pulse in response to a first transition of the clock signal; and

a clocked comparator coupled to the one-shot circuit and operative to receive the pulse, the clocked comparator determining the state of the slew rate control signal by sampling for the presence of the pulse in response to a second transition of the clock signal.

2. The driver circuit of claim 1, wherein the slew rate control signal is asserted when the pulse is detected when the clocked comparator samples for the presence of the pulse, and the slew rate control signal is not asserted when the pulse is not detected when the clocked comparator samples for the presence of the pulse.

3. A driver circuit having a controlled slew rate comprising:

a first circuit having an input coupled to receive a data signal and an output operative to output a drive signal in response to the data signal;

a second circuit coupled in parallel with the first circuit and operative to receive a plurality of slew rate control signals; and

a slew rate indicator circuit coupled to the second circuit, the slew rate indicator circuit determining the state of the plurality of slew rate controls signal in response to operating conditions that cause variations in the slew rate of the drive signal such that when the plurality of slew rate control signals are asserted, then the second circuit is enabled to affect the slew rate of the drive signal, and wherein the slew rate indicator circuit comprises;

a plurality of pulse generator circuits coupled to receive a trigger signal, each of the pulse generator circuits generating a pulse in response to the trigger signal; and

a plurality of clocked comparator circuits each coupled to receive one of the plurality of pulses and one of a plurality of sampling signals, wherein the clocked comparators circuits determine the state of the slew rate control signals by sampling for the presence of the plurality of pulses in response to the plurality of sampling signals.

4. The driver circuit of claim 3, wherein the plurality of sampling signals are asserted a predetermined time after the trigger signal is asserted.

5. The driver circuit of claim 3, wherein the plurality of clocked comparator circuits generate a plurality of code signals in response to sampling for the presence of the plurality of pulses, and wherein the slew rate indicator circuit further comprises a combinational logic circuit receiving the plurality of code signals and generating the plurality of slew rate control signals.

6. The driver circuit of claim 3, wherein one of the pulse generator circuits comprises a one-shot circuit.

7. The driver circuit of claim 6, wherein the one-shot circuit comprises a plurality of transistors, wherein each of the transistors is the same type of transistor.

8. A driver circuit having a controlled slew rate comprising:

a first circuit having an input coupled to receive a data signal and an output operative to output a drive signal in response to the data signal;

a second circuit coupled in parallel with the first circuit and operative to receive a plurality of slew rate control signals; and

a slew rate indicator circuit coupled to the second circuit, the slew rate indicator circuit determining the state of the slew rate control signals in response to operating conditions that cause variations in the slew rate of the drive signal such that when the slew rate control signals are asserted, then the second circuit is enabled to affect the slew rate of the drive signal, the slew rate indicator circuit comprising a code generator having a plurality of tracking circuits that generate a code in response to changes in the operating conditions that cause variations in the slew rate of the drive signal, wherein each tracking circuit comprises;

a current source coupled to a node;

a biasing transistor coupled to the node; and

a comparator having a first input coupled to the node and a second input coupled to a reference voltage, wherein the comparator outputs a bit of the code.

9. A method for controlling a slew rate of a driver signal of a driver circuit comprising;

generating an active state and an inactive state of a pulse signal in response to a first transition of a trigger signal;

comparing the pulse signal with a reference voltage a first predetermined time after the first transition of the trigger signal; and

adjusting the slew rate of the driver signal when the pulse signal is in the active state at the first predetermined time after the first transition of the trigger signal.

10. The method of claim 9, further comprising the step of not adjusting the slew rate of the drive signal when the signal is in an inactive state at the first predetermined time after the first transition of the trigger signal.

11. The method of claim 9, wherein the comparing step comprises sampling the signal in response to a second transition of the trigger signal.

12. The method of claim 9, further comprising the steps of:

generating a code signal in response to the comparing step; and

translating the code signal into a slew rate control signal, wherein the adjusting step adjusts the slew rate of the driver signal in response to the slew rate control signal.

13. A method for controlling a slew rate of a driver signal of a driver circuit comprising:

generating a pulse in response to a first transition of a trigger signal;

sampling for the pulse at a first predetermined time after the first transition of the trigger signal; and

adjusting the slew rate of the drive signal when the pulse is in a first state at the first predetermined time after the first transition of the trigger signal, and further adjusting a duty cycle of the drive signal.

14. A driver circuit having slew rate control comprising:

a first drive circuit operative to output a drive signal;

a pulse generator operative to generate a pulse in response to a first transition of a trigger signal;

a comparator circuit having a first input and a second input, the first input for receiving the pulse from the pulse generator, and the second input coupled to a reference voltage, the comparator circuit operative to generate a slew rate control signal in response to comparing the signals at its first and second inputs; and

a second drive circuit coupled to the first drive circuit and receiving the slew rate control signal from the comparator circuit, wherein the second drive circuit affects the slew rate of the drive signal in response to the slew rate control signal.

18. The driver circuit of claim 14, wherein the comparator circuit is operative to compare the signals at its first and second inputs in response to a second transition of the trigger signal.

15. A process-voltage-temperature (PVT) detector circuit comprising:

a pulse generator circuit operative to generate a pulse in response to a first transition of a clock signal; and

a clocked comparator having a first input, a second input, and a third input, the first input for receiving the pulse from the pulse generator circuit, the second input coupled to a reference voltage, and the third input for receiving the clock signal, the clocked comparator configured to compare the signals at the first and second inputs and generate a control signal in response to a second transition of the clock signal, wherein the control signal indicates the PVT operating conditions of the PVT detector circuit.

16. A process-voltage-temperature (PVT) detector circuit comprising:

a first pulse generator coupled to receive a trigger signal, the first pulse generator comprising an n-channel MOS transistor and configured to generate a first pulse having a pulse width determined by affects of PVT operating conditions on the n-channel MOS transistor;

a second pulse generator coupled to receive the trigger signal, the second pulse generator comprising a p-channel MOS transistor and configured to generate a second pulse having a pulse width determined by affects of PVT operating conditions on the p-channel MOS transistor;

a first comparator having first, second, and third inputs, the first input for receiving the first pulse from the first pulse generator, the second input coupled to a first reference voltage, and the third input coupled to a first sampling signal, the first comparator operative to compare the signals at the first and second input and generate a first control signal in response to the first sampling signal, wherein the first control signal indicates the affect of the PVT operating conditions on the n-channel MOS transistor; and

a second comparator having first, second, and third inputs, the first input for receiving the second pulse from the second pulse generator, the second input coupled to a second reference voltage, and the third input coupled to a second sampling signal, the second comparator operative to compare the signals at the first and second input and generate a second control signal in response to the second sampling signal, wherein the second control signal indicates the affect of the PVT operating conditions on the p-channel MOS transistor.

17. The PVT detector circuit of claim 16, wherein the first and second reference voltages are the same reference voltage.