Force sensing resistor conditioning circuit

• US 5,959,538 A
• Filed: 10/15/1997
• Issued: 09/28/1999
• Est. Priority Date: 10/15/1997
• Status: Expired due to Term

• Current Assignee: Vital Innovations Limited
• Original Assignee: Vital Innovations Limited
• Inventors: Schousek, Brian Walter
• Primary Examiner(s): Lee, Benjamin C.
• Application Number:
  US08/951,145
• Time in Patent Office: 713 Days
• Field of Search: 340/665, 340/635, 340/501, 324/601, 324/609, 324/691
• US Class Current: 340/665
• CPC Class Codes: G01D 5/16 by varying resistance
• CPC Class Codes: G01K 7/24 in a specially-adapted circuit, e.g. bridge circuit
• CPC Class Codes: G01L 1/22 using resistance strain gauges

Abstract

The present invention discloses a circuit for providing a variable output signal in response to a physical parameter sensed by a sensor in the circuit, preferably a force sensing resistor. The current mirror may consist of two transistors having common bases. Flow of current through the first transistor flows through the sensor and through a parallel resistor. This current is mirrored in a second transistor which provides flow of current which may either be used as an output signal or, more preferably, as a base current for a transistor which is used to control output signal voltage. The circuit uses the current mirror in connection with the sensor to eliminate the need for a negative voltage supply. The circuit may further advantageously contain a voltage limiter module which is used to limit the voltage which may be applied across the sensor if the range of input signals or the desired range of output signals exceeds the sensor'"'"'s capability. The voltage limiter module establishes a fixed voltage across the sensor which is lower than the expected input or the desired output voltage ranges. The resistor in parallel with the sensor is used to ensure that a current is applied to the transistor in the voltage limiter module so that the transistor may maintain its operation as an emitter follower. The circuit may also be used with thermistors for temperature compensation.

Claims

1. A physical parameter sensing circuit, comprising:

a) a current mirror module having an input node and a first and second output node, said input node connectable to a power source, said second output node configured to follow current of said first output node;

b) a physical parameter responsive circuit element comprising a variable resistance sensor and having a first connection at said first output node of said current mirror to change the current at said first output node substantially proportional to the physical parameter;

wherein said second output node acts as an output signal point for said circuit indicative of the physical parameter.

2. The circuit of claim 1 wherein said physical parameter responsive circuit element comprises a force sensing resistor.

3. The circuit of claim 1 wherein said physical parameter responsive circuit element further comprises a grounded second connection.

4. The circuit of claim 1 wherein said physical parameter responsive circuit element further comprises a voltage controlled second end.

5. The circuit of claim 1 further comprising a first resistive component in parallel with said physical parameter responsive circuit element.

6. The circuit of claim 1 further comprising a voltage limiter, said voltage limiter configured to limit voltage which can be applied across said physical parameter responsive circuit element by a power source.

7. The circuit of claim 1 further comprising an output buffer, said output buffer connected to said second output node and configured to buffer said circuit from loads which may be connected to said output signal.

8. The circuit of claim 1 wherein said current mirror comprises a first b-j-t mirror transistor and a second b-j-t mirror transistor, said first and said second mirror transistors having a common connection at their bases and a common connection at said input node.

9. The circuit of claim 8 wherein said emitters of said first and said second mirror transistors are connected in common at said input node.

10. The circuit of claim 8 wherein said force sensing resistor is connected to the collector of said first mirror transistor.

11. The circuit of claim 8 wherein said first and said second mirror transistors are PNP transistors.

12. The circuit of claim 8 wherein said first and said second mirror transistors are NPN transistors.

13. The circuit of claim 8 wherein said first mirror transistor output is connected to said first output node and said second mirror transistor output connected to is said second output node.

14. The circuit of claim 8 wherein said first mirror transistor output is connected to said bases of said first and said second mirror transistors.

15. The circuit of claim 13 wherein said current mirror further comprises a first mirror resistor in parallel with said second output node.

16. The circuit of claim 15 wherein said mirror resistor is grounded.

17. The circuit of claim 6 wherein said voltage limiter is connected to said input node in parallel with said current mirror.

18. The circuit of claim 6 wherein said voltage limiter comprises a diode.

19. The circuit of claim 6 wherein said voltage limiter comprises a limiter resistive component in parallel with said current mirror and a current sensitive element in series with said physical parameter responsive circuit element, said current sensitive element receiving controlling current from said limiter resistive component.

20. The circuit of claim 19 wherein said limiter resistive component comprises a resistor divider.

21. The circuit of claim 19 wherein said current sensitive element comprises a b-j-t limiter transistor, said limiter transistor base connected to said second resistive component.

22. The circuit of claim 21 wherein said resistor divider comprises in parallel a second resistor and a third resistor, and wherein said base of said limiter transistor is connected between said second and said third resistors.

23. The circuit of claim 21 further comprising a first resistive component disposed between said force sensing resistor and said limiter transistor input.

24. The circuit of claim 21 wherein said limiter transistor functions as an emitter-follower.

25. The circuit of claim 24 wherein said limiter transistor comprises a PNP transistor.

26. The circuit of claim 24 wherein said limiter transistor comprises a NPN transistor.

27. The circuit of claim 19 wherein said current sensitive element comprises a Zener diode.

28. The circuit of claim 20 wherein said limiter resistive component comprises a Zener diode.

29. The circuit of claim 7 wherein said output buffer comprises a b-j-t buffer transistor having its base connected to said second output node.

30. The circuit of claim 29 wherein the emitter of said buffer transistor is connected to said output signal point.

31. The circuit of claim 29 wherein the collector of said buffer transistor is connected to said input node.

32. The circuit of claim 19 wherein said output buffer comprises a buffer resistive component in parallel with said output signal point.

33. The circuit of claim 32 wherein said buffer resistive component is grounded.

34. The circuit of claim 8 wherein said first and said second mirror transistors comprise a monolithic transistor pair.

35. The circuit of claim 1 wherein said current mirror comprises an integrated circuit current mirror.

36. The circuit of claim 1 wherein said current mirror module and said physical parameter responsive circuit element are mounted on a printed circuit board, and wherein said printed circuit board is encased in a resilient material.

37. A force responsive circuit comprising:

a) a current mirror module having an input node and a first and second output node, said input node connectable to a power source, said second output node configured to follow current of said first output node;

b) a force responsive module providing a variable output signal indicative of an applied force and having a first force module node connected to said first output node of said current mirror, and a second force module node;

c) a voltage limiter module, said voltage limiter module having a first voltage limiter node connected to said input node, and a second voltage limiter node connected to said second force module node, said voltage limiter module configured to limit voltage which can be applied across said force responsive module by a power source; and

d) an output buffer, said output buffer having a first buffer node connected to said input node, a second buffer node connected to said second output node, and a buffer output node, said output buffer configured to buffer said circuit from loads which are adapted to be connected to said buffer output node,

wherein said buffer output node acts as an output signal point for said circuit.

38. The circuit of claim 37 wherein said current mirror module comprises a pair of parallel b-j-t mirror transistors having commonly connected bases, emitters commonly connected to said input node, a first emitter connected to said first output node, and a second emitter connected to said second output node.

39. The circuit of claim 38 wherein said current mirror module further comprises a first current mirror resistor connected to and in parallel with said second output node.

40. The circuit of claim 37 wherein said force responsive module comprises a force sensitive resistor.

41. The circuit of claim 40 wherein said force sensitive resistor is configured to decrease current resistance in response to increased pressure being applied to said force sensitive resistor.

42. The circuit of claim 40 wherein said force responsive module further comprises a first force module resistor in parallel with said force sensitive resistor.

43. The circuit of claim 37 wherein said output buffer comprises a b-j-t buffer transistor having a collector connected to said first buffer node, a base connected to said second output node, and an emitter connected to said buffer output node.

44. The circuit of claim 43 wherein said output buffer further comprises a buffer resistor connected in parallel to said buffer output node.

45. The circuit of claim 37 wherein said voltage limiter module comprises a diode.

46. The circuit of claim 37 wherein said voltage limiter module comprises:

a. a serial resistor divider connected to said first voltage limiter node, said resistor divider causing a first divider voltage and a second divider voltage in response to a voltage being applied across said resistor divider; and

b. a voltage limiter b-j-t transistor having an emitter connected to said second voltage limiter node, and a base and collector connected across said second divider voltage.

47. Method of generating a voltage output signal spanning an input voltage in response to a variable force input, comprising:

a) providing a first current produced by said input voltage through a physical parameter sensor, said sensor varying resistance and said first current in response to the variable force input sensed by said sensor;

b) producing a second current in response to and equal to said first current using a current mirror circuit, and providing said second current to an output load to produce said output voltage signal indicative of said variable force input.

48. The method of claim 47 further comprising the steps of:

a. limiting the voltage which may be applied across said force sensor by causing part of said input voltage to be placed across a voltage limiter; and

b. using said second current to control a larger current which may be used to generate said output signal.

49. A temperature compensating circuit, comprising:

a) a current mirror module having an input node and a first and second output node, said input node connectable to an input source, said second output node configured to follow current of said first output node;

b) a thermistor device having a first connection at said first output node of said current mirror to change current at said first output node substantially proportional to the thermistor device output;

wherein said second output node acts as an output signal point for said circuit.

50. The circuit of claim 49 further comprising a voltage limiter, said voltage limiter configured to limit voltage which can be applied across said thermistor device by a power source.

51. The circuit of claim 49 further comprising an output buffer, said output buffer connected to said second output node and configured to buffer said circuit from loads which are adapted to be connected to said output signal.