Pixel buffer circuits for implementing improved methods of displaying grey-scale or color images

• US 5,959,598 A
• Filed: 02/09/1996
• Issued: 09/28/1999
• Est. Priority Date: 07/20/1995
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: The Board of Regents of the University of Colorado (University of Colorado System)
• Inventors: McKnight, Douglas J.
• Primary Examiner(s): Hjerpe, Richard A.
• Assistant Examiner(s): Chang, Kent
• Application Number:
  US08/605,999
• Time in Patent Office: 1,327 Days
• Field of Search: 345/90, 345/92, 345/98, 345/87, 345/99, 345/147
• US Class Current: 345/90
• CPC Class Codes: G06T 3/40 Scaling of whole images or parts thereof, e.g. expanding or contracting
• CPC Class Codes: G09G 2300/0809 Several active elements per pixel in active matrix panels
• CPC Class Codes: G09G 2300/0814 used for selection purposes, e.g. logical AND for partial update
• CPC Class Codes: G09G 2300/0823 used to establish symmetry in driving, e.g. with polarity inversion
• CPC Class Codes: G09G 2300/0828 forming a digital to analog [D/A] conversion circuit
• CPC Class Codes: G09G 2300/0842 forming a memory circuit, e.g. a dynamic memory with one capacitor
• CPC Class Codes: G09G 2300/0847 being a dynamic memory without any storage capacitor, i.e. with use of parasitic capacitances as storage elements
• CPC Class Codes: G09G 2300/0857 Static memory circuit, e.g. flip-flop
• CPC Class Codes: G09G 2310/0235 Field-sequential colour display
• CPC Class Codes: G09G 2310/0251 Precharge or discharge of pixel before applying new pixel voltage
• CPC Class Codes: G09G 2320/0233 Improving the luminance or brightness uniformity across the screen
• CPC Class Codes: G09G 2320/0247 Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
• CPC Class Codes: G09G 2320/0266 Reduction of sub-frame artefacts
• CPC Class Codes: G09G 2320/0633 by amplitude modulation of the brightness of the illumination source
• CPC Class Codes: G09G 2320/064 by time modulation of the brightness of the illumination source
• CPC Class Codes: G09G 3/20 for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
• CPC Class Codes: G09G 3/2011 by amplitude modulation
• CPC Class Codes: G09G 3/2014 by modulation of the duration of a single pulse during which the logic level remains constant
• CPC Class Codes: G09G 3/2018 by time modulation using two or more time intervals
• CPC Class Codes: G09G 3/2022 using sub-frames
• CPC Class Codes: G09G 3/2033 : with splitting one or more sub-frames corresponding to the most significant bits into two or more sub-frames
• CPC Class Codes: G09G 3/2037 : with specific control of sub-frames corresponding to the least significant bits
• CPC Class Codes: G09G 3/3406 : Control of illumination source illumination devices structurally associated with liquid crystal cells G02F1/1336
• CPC Class Codes: G09G 3/3648 : using an active matrix G09G3/367 - G09G3/3696 take precedence
• CPC Class Codes: G09G 3/3659 : the addressing of the pixel involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependant on signal of two data electrodes

Abstract

A device such as a display device or a spatial light modulator can store pixel data in a plurality of small circuits coupled to pixel mirrors and simultaneously drive these pixel mirrors a frame at a time. This device is particularly beneficial for implementing improved image quality techniques which can convert binary images to grey-scale images and/or separate red, green and blue images into color images and displaying those images using the natural process of integration which occurs when a person views images at sufficiently high rates.

Claims

1. A device, comprising:

a substrate having a first surface;

a plurality of driving electrodes arranged on said first surface of the substrate; and

a plurality of circuits arranged on said substrate and respectively coupled to said plurality of driving electrodes, for receiving and storing image data and for driving said plurality of driving electrodes a frame at a time synchronous with a switching signal;

wherein each of said plurality of circuits comprises;

a first switch coupled to a gate signal and a data line for receiving a pixel datum of said image data and outputting said pixel datum in accordance with said gate signal,

a first inverter coupled to said first switch for receiving said pixel datum;

a second switch coupled to a clock signal and said first inverter, and

a second inverter coupled to said second switch and to a respective one of said plurality of driving electrodes, wherein said pixel datum is transmitted from said first inverter to said second inverter synchronous with said clock signal, and outputs said pixel datum to said respective one of the plurality of driving electrodes.

2. The device as claimed in claim 1, further comprising a liquid crystal layer arranged on said first surface.

3. The display device as claimed in claim 2, further comprising a window arranged on said liquid crystal layer, wherein said plurality of means comprises a plurality of storage elements capable of approximately simultaneously outputting said image data to said driving electrodes which drive said liquid crystal layer to yield an image.

4. The display device as claimed in claim 1, wherein said first switch comprises a first transistor and said second switch comprises a second transistor.

5. The display device as claimed in claim 4, wherein said first and second transistors are FETs.

6. The display device as claimed in claim 1, wherein said first switch comprises a first pair of FETs and said second switch comprises a second pair of FETs.

7. The device as claimed in claim 1, further comprising a liquid crystal layer arranged on said first surface.

8. The device as claimed in claim 1, further comprising a first switch coupled to a gate signal and a data line for receiving a pixel datum of said data and outputting said pixel datum in accordance with said gate signal.

9. The device as claimed in claim 8, further comprising capacitance means coupled to said first switch for receiving and storing said pixel datum.

10. The device as claimed in claim 9, further comprising a second switch coupled to a clock signal and said capacitance means.

11. The device as claimed in claim 10, further comprising a second switch coupled to a clock signal and said capacitance means.

12. The device as claimed in claim 11, further comprising an inverter which receives and outputs a pixel datum to said respective one of the plurality of driving electrodes.

13. The device as claimed in claim 1, wherein said plurality of means receives image data comprising a series of subframes.

14. The device as claimed in claim 13, wherein said plurality of means receives image data comprising a series of color subframes to be displayed in series at sufficiently high frame rates to produce color integration of images to an observer.

15. The device as claimed in claim 13, wherein said plurality of means receives image data comprising a series of binary subframes to be displayed in series at sufficiently high frame rates to produce grey-scale integration of images to an observer.

16. The device as claimed in claim 1, wherein said substrate comprises a spatial light modulator which is driven by said plurality of driving electrodes.

17. The device as claimed in claim 1, further comprising a liquid crystal layer arranged on said first surface which is driven by said plurality of driving electrodes.

21. The device as claimed in claim 13, wherein said plurality of means receives image data comprising a series of analog color subframes.

22. The device as claimed in claim 14, wherein said plurality of means receives image data comprising a series of binary color subframes.

18. A device comprising:

a substrate having a first surface;

a plurality of driving electrodes arranged on said first surface of the substrate; and

a plurality of circuits arranged on said substrate and respectively coupled to said plurality of driving electrodes, for receiving and storing image data and for driving said plurality of driving electrodes a frame at a time synchronous with a switching signal;

wherein each of said plurality of circuits comprises;

a first switch coupled to a gate signal and a data line for receiving a pixel datum of said image data and outputting said pixel datum in accordance with said gate signal,

a capacitance means coupled to said first switch for receiving and storing said pixel datum,

a second switch coupled to a clock signal and said first inverter, and

an inverter coupled to said second switch and to a respective one of said plurality of driving electrodes, wherein said pixel datum is transmitted from said capacitor means to said inverter synchronous with said clock signal, and which outputs said pixel datum to said respective one of the plurality of driving electrodes.

19. The device as claimed in claim 18, wherein said capacitance means comprises a capacitor.

20. The device as claimed in claim 18, further comprising a liquid crystal layer arranged on said first surface.

23. A device, comprising:

a substrate having a first surface;

a plurality of driving electrodes arranged on said first surface of the substrate; and

a plurality of circuits arranged on said substrate and respectively coupled to said plurality of driving electrodes, for receiving and storing image data and for driving said plurality of driving electrodes a frame at a time synchronous with a switching signal;

wherein each of said plurality of circuits comprises;

a first switch coupled to a gate signal and a data line for receiving a pixel datum of said image data and outputting said pixel datum in accordance with said gate signal,

a capacitance means coupled to said first switch for receiving and storing said pixel datum,

a second switch coupled to a global pull-up signal and said capacitance means, and

an electrode driver coupled to said second switch and to a respective one of said plurality of driving electrodes, wherein said pixel datum is transmitted from said capacitor means to said electrode driver synchronous with said global pull-up signal, and which outputs said pixel datum to said respective one of the plurality of driving electrodes.

24. The device as claimed in claim 23, wherein said pixel datum comprises an analog quantity.

25. The device as claimed in claim 23, wherein said electrode driver comprises a voltage limiting transistor and said pixel datum comprises an analog quantity.

26. The device as claimed in claim 23, further comprising a third switch coupled to a global pull-down signal and a respective one of the plurality of driving electrodes, wherein said driving electrodes are reset synchronous with said global pull-down signal.