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Active matrix type liquid-crystal display unit and method of driving the same

  • US 5,959,599 A
  • Filed: 11/04/1996
  • Issued: 09/28/1999
  • Est. Priority Date: 11/07/1995
  • Status: Expired due to Term
First Claim
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1. An in-plane switching type active matrix type liquid-crystal display unit comprising:

  • first and second scanning lines that do not intersect with each other;

    a data line that intersects with said first and second scanning lines;

    an earth line that intersects with said first and second scanning lines but does not intersect with said data line;

    a pair of first and second electrodes that hold liquid crystal therebetween; and

    first to fourth switching circuits, in which said first and second electrodes and said first to fourth switching circuits are disposed in a region surrounded by said first and second scanning lines, said data line and said earth line, and are disposed on the same substrate;

    wherein said first to fourth switching circuits include a circuit having at least one transistor connected in series, respectively;

    wherein in transistors connected in series in said first switching circuit, a source of a first transistor is connected to said data line, gates of all the transistors are connected to said first scanning line;

    wherein in transistors connected in series in said second switching circuit, a source of a first transistor is connected to said earth line, gates of all the transistors are connected to said second scanning line;

    wherein in said first and second switching circuits, drains of final transistors are connected to said first electrode, respectively;

    wherein in transistors connected in series in said third switching circuit, a source of a first transistor is connected to said date line, gates of all the transistors are connected to said second scanning line;

    wherein in transistors connected in series in said fourth switching circuit, a source of a first transistor is connected to said earth line, gates of all the transistors are connected to said first scanning line; and

    wherein in said third and fourth switching circuits, drains of final transistors are connected to said second electrode, respectively.

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