Method and apparatus for constructing a frame buffer with a fast copy means

• US 5,959,638 A
• Filed: 03/22/1996
• Issued: 09/28/1999
• Est. Priority Date: 08/13/1993
• Status: Expired due to Term

• Current Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Frank, Edward H., Forrest, Craig S., Naughton, Patrick J.
• Primary Examiner(s): Chow, Dennis-Doon
• Application Number:
  US08/620,279
• Time in Patent Office: 1,285 Days
• Field of Search: 345/185, 345/189, 345/200, 345/201, 345/203, 345/113, 345/114, 345/507, 345/509, 345/515, 345/508, 345/511, 345/512, 345/115, 345/473, 345/949, 345/951, 345/952, 345/953 , 345/516, 395/501, 395/507, 395/508, 395/509, 395/511, 395/512, 395/514, 395/520, 395/521, 395/522, 395/526, 395/524, 395/525
• US Class Current: 345/537
• CPC Class Codes: G09G 5/393 Arrangements for updating the contents of the bit-mapped memory

Abstract

A method and apparatus for quickly copying a first frame region into a second frame region. A video memory array comprising a plurality of video random access memory devices is divided into at least two frame regions. A background image is rendered by a central processing unit into a background frame region within the video memory array. The central processing unit then requests the background image in the background frame region to be copied into a new frame region in the video memory array. A dedicated circuit copies the entire background image in the background frame region into the new frame region. The dedicated circuit operates by using a serial data register within each video random access memory device during the vertical retrace period of a video timing signal. The dedicated circuit performs the background frame copy without requiring any processing resources from the central processing unit.

Claims

1. In a computer system, a frame buffer apparatus for copying video information, said frame buffer apparatus comprising:

a video memory array divided into at least three frame regions including a first frame region associated with a background display image frame, a second frame region associated with a future display image frame, and a third frame region associated with a current display image frame, said video memory array including at least one video random access memory device having a plurality of memory locations and a data register capable of loading and storing a row of said memory locations in said video random access memory device; and

a copy apparatus coupled to said video memory array including means for loading and storing a plurality of rows of said memory locations using said data register in each video random access memory device to copy said background display image frame in first frame region in said video memory array to said future display image frame in second frame region in said video memory array, wherein said copy apparatus does not copy data to the third frame region while associated with a current display image frame.

2. The frame buffer apparatus as claimed in claim 1 wherein said frame buffer apparatus generates a video timing signal, said video timing signal having a vertical retrace period, and said copy apparatus operates only during said vertical retrace period.

3. The frame buffer apparatus as claimed in claim 1 wherein said frame buffer apparatus generates a video timing signal, said video timing signal having a horizontal retrace period, and said copy apparatus operates only during said horizontal retrace period.

4. The frame buffer apparatus as claimed in claim 1 wherein said frame buffer apparatus includes

means for generating a video timing signal having a vertical retrace period and a horizontal retrace period, and,

wherein said copy apparatus includes

means for only operating during at least one of said vertical retrace period and said horizontal retrace period.

5. The frame buffer apparatus as claimed in claim 2 wherein said data register that can load and store a row of said memory locations in said video random access memory device comprises a serial data register coupled to serial access port.

6. In a computer system, a frame buffer apparatus for managing image frames, said frame buffer apparatus comprising:

a video memory array divided into a first frame region associated with first display image frame, a second frame region associated with second display image frame, and a third frame region associated with third display image frame, said video memory array including at least one video random access memory device having a plurality of memory locations and a serial data register capable of loading and storing a row of said memory locations in said video random access memory device;

a copy apparatus coupled to said video memory array, said copy apparatus including

means for loading and storing a plurality of rows of said memory;

a background frame register storing a pointer to one of the frame regions in said video memory array;

a future frame register storing a pointer to one of the frame regions in said video memory array;

locations using said data register in each video memory device to copy contents in said frame region pointed to by the background frame register to said frame region pointed to by the future frame register;

a display frame register storing a pointer to one of the frame regions in said video memory array; and

a video display circuit including

means for loading rows of memory from the frame region pointed to by said display frame register into said serial data register and shifting said rows of memory out through a serial access port connected to serial data register.

7. The frame buffer apparatus as claimed in claim 6 wherein said frame buffer apparatus further comprises:

a background frame register, said background frame register pointing to a background frame region in said video memory array containing a background image;

a new frame register, said new frame register pointing to a new frame region in said video memory array; and

wherein said copy apparatus copies from said background frame region to said new frame region.

8. The frame buffer apparatus as claimed in claim 7 wherein said frame buffer apparatus further comprises a copy control bit and said frame buffer apparatus copies from said background frame region to said new frame region when said copy control bit is set by a central processing unit.

9. The frame buffer apparatus as claimed in claim 8 wherein each video random access memory device in said memory array comprises a random access port such that said central processing unit can access each memory location in said video random access memory array.

10. In a computer system, a frame buffer apparatus for copying information, said frame buffer apparatus comprising:

memory means divided into at least three frame regions, a first frame region associated with a background display image frame, a second frame region associated with a future display image frame, and a third frame region associated with a current display image frame, said memory means having a plurality of memory locations and a data register capable of loading and storing a row of said memory locations in said memory means; and

copy means coupled to said memory means, said copy means including means for loading and storing a plurality of rows of said memory locations using said data register in said memory means to copy said background display image frame in first frame region in said video memory array to said future display image frame in second frame region in said memory means, wherein said copy means does not copy data to the third frame region while associated with a current display image frame.

11. The frame buffer apparatus as claimed in claim 10 wherein said frame buffer apparatus generates a video timing signal, said video timing signal having a vertical retrace period, and said copy means operates only during said vertical retrace period.

12. The frame buffer apparatus as claimed in claim 10 wherein said frame buffer apparatus generates a video timing signal, said video timing signal having a horizontal retrace period, and said copy apparatus operates only during said horizontal retrace period.

13. The frame buffer apparatus as claimed in claim 10 wherein said frame buffer apparatus includes

means for generating a video timing signal having a vertical retrace period and a horizontal retrace period, and,

wherein said copy apparatus includes

means for operating in at least one of said vertical retrace period and said horizontal retrace period.

14. The frame buffer apparatus as claimed in claim 11 wherein said data register that can load and store a row of said memory locations in said means comprises a serial data register coupled to serial access port.

15. In a computer system, a frame buffer apparatus for copying video information in a first frame region, said frame buffer apparatus comprising:

memory means divided into the first frame region associated with a first display image frame, a second frame region associated with a second display image frame, and a third display frame region associated with a third display image frame, said memory means including a plurality of memory locations and a data register capable of loading and storing a row of said memory locations in said memory means;

a background frame register storing a pointer to one of the frame regions in said video memory array;

a future frame register storing a pointer to one of the frame regions in said video memory array;

copy means coupled to said memory means, said copy means loading and storing a plurality of rows of said memory locations using said data register in said memory means to copy contents in the frame region pointed to by the background frame register to said frame region pointed to by the future frame register;

display frame register storing a pointer to one of the display frame regions in said video memory array; and

video display means including

means for loading rows of memory from a display frame region pointed to by said display frame register means into said serial data register and shifting said rows of memory out through said serial access port.

16. The frame buffer apparatus as claimed in claim 15 wherein said frame buffer apparatus further comprises:

background frame register means, said background frame register means pointing to a background frame region in said video memory array containing a background image;

a new frame register means, said new frame register means pointing to a new frame region in said video memory array; and

wherein said copy means copies from said background frame region to said new frame region.

17. The frame buffer apparatus as claimed in claim 16 wherein further comprises a copy control bit and said copy means copies from said background frame region to said new frame region when a central processing unit sets said copy control bit.

18. In a graphic computer system, said graphic computer system comprising a graphics display screen and a copy apparatus for copying one frame region associated with a background display image frame to a second frame region associated with a future display image frame, a method of performing doubled buffered animation, said method comprising the steps of:

a) painting a background scene in a background frame region;

b) copying said background scene in said background frame region into a first frame region using said copy apparatus;

c) rendering a frame of animation in said first frame region, said frame of animation rendered on said background scene;

d) displaying said first frame region on said graphics display screen;

e) copying said background scene in said background frame region into a second frame region using said copy apparatus;

f) rendering a frame of animation in said second frame region, said frame of animation rendered on said background scene;

g) displaying said second frame region on said graphics display screen; and

h) repeating steps b through g until said animation is complete.

19. The method of performing doubled buffered animation as claimed in claim 18 wherein said steps of copying are performed during a vertical retrace period of a video timing signal.

20. The method of performing doubled buffered animation as claimed in claim 18 wherein said steps of copying are performed during a horizontal retrace period of a video timing signal.

21. The method of performing doubled buffered animation as claimed in claim 18 wherein said steps of copying are performed during a vertical retrace and a horizontal retrace period of a video timing signal.

22. The method of performing doubled buffered animation as claimed in claim 18 wherein said method of performing doubled buffered animation is performed in real time.

23. A method of copying video information with a frame buffer apparatus in a computer system including a video memory array having at least one random access memory device with a plurality of memory locations and a serial data register, said method comprising:

dividing said video memory array into a first frame region associated with a background display image frame, a second frame region associated with a future display image frame, and a third frame region associated with a current display image frame;

copying contents in the first frame region to the second frame region by loading and storing a plurality of rows of said memory locations in each random access memory device using said serial data register; and

changing an association of the current display image frame from the third frame region to one of the first and second frame regions.

24. The method according to claim 23, wherein said frame buffer apparatus further comprises the step of

generating a timing signal having a vertical retrace period and a horizontal retrace period.

25. The method according to claim 24, wherein said step of copying further comprises the step of

copying contents from said first frame region to second frame region during at least one of vertical retrace period and horizontal retrace period.

26. The method according to claim 25, wherein said frame buffer apparatus further comprises the step of

pointing to a display frame region in said video memory array;

loading rows of memory from said display frame region into said serial data register; and

shifting rows of memory out through a serial access port coupled to said serial data register.