Asymmetrical duty cycle flyback converter

• US 5,959,850 A
• Filed: 11/16/1998
• Issued: 09/28/1999
• Est. Priority Date: 11/18/1997
• Status: Expired due to Fees

• Current Assignee: Samsung Electro-Mechanics Co., Ltd. (Samsung Group)
• Original Assignee: Samsung Electro-Mechanics Co., Ltd. (Samsung Group)
• Inventors: Lim, Sung Ho
• Primary Examiner(s): BERHANE, ADOLF D
• Application Number:
  US09/192,681
• Time in Patent Office: 316 Days
• Field of Search: 363/17, 363/24, 363/25, 363/56, 363/95, 363/97, 363/98, 363/124, 363/131, 363/132, 363/134
• US Class Current: 363/17
• CPC Class Codes: H02M 3/01 Resonant DC/DC converters
• CPC Class Codes: H02M 3/33571 Half-bridge at primary side of an isolation transformer

Abstract

An asymmetrical duty cycle flyback converter comprising a main transformer for transforming an input voltage at a desired ratio, the main transformer including a primary winding connected to an input stage and a secondary winding connected to an output stage, a switching circuit for switching the input voltage to the main transformer, the switching circuit including first and second switches, a rectifying/smoothing circuit for rectifying and smoothing an output voltage from the main transformer, a controller for generating a control signal in response to an output voltage from the rectifying/smoothing circuit to control the switching operation of the switching circuit, and a switch driver for generating first and second drive signals in response to the control signal from the controller to drive the first and second switches in the switching circuit in such a manner that they can complementarily be switched on the basis of on-time duties asymmetrical with respect to each other and at an interval of a dead time therebetween to perform a zero voltage switching operation. With this construction, the present invention has the effect of realizing a miniaturation and improvement in power efficiency.

Claims

1. An asymmetrical duty cycle flyback converter comprising:

a main transformer for transforming an input voltage at a desired ratio, said main transformer including a primary winding connected to an input stare and a secondary winding connected to an output stage;

switching means for switching said input voltage to said main transformer, said switching means including first and second switches;

rectifying/smoothing means for rectifying and smoothing an output voltage from said main transformer;

control means for generating a control signal in response to an output voltage from said rectifying/smoothing means to control the switching operation of said switching means; and

switch driving means for generating first and second drive signals in response to said control signal from said control means to drive said first and second switches in said switching means in such a manner that they can be switched complementarily on the basis of on-time duties asymmetrical with respect to each other and at an interval of a dead time therebetween to perform a zero voltage switching operation,

wherein said first and second switches in said switching means include, respectively, first and second field effect transistors connected in series between said input stage and a around voltage source, and

wherein said switch driving means includes;

first delay means for delaying said control signal from said control means for a first predetermined time period;

first comparison means for comparing the level of an output signal from said first delay means with that of a first reference voltage signal and providing its output signal only when said output signal from said first delay means is higher in level than said first reference voltage signal;

first buffering means for buffering said output signal from said first comparison means and applying the buffered signal to a gate of said first field effect transistor in said switching means;

electric isolation means for electrically isolating said first field effect transistor from an output signal from said first buffering means;

second delay means for delaying said control signal from said control means for a second predetermined time period;

second comparison means for comparing the level of an output signal from said second delay means with that of a second reference voltage signal and providing its output signal only when said output signal from said second delay means is lower in level than said second reference voltage signal; and

second buffering means for buffering said output signal from said second comparison means and applying the buffered signal to a gate of said second field effect transistor in said switching means.

2. An asymmetrical duty cycle flyback converter as set forth in claim 1, wherein said primary winding of said main transformer has its one side connected to a node between said first and second field effect transistors and its other side connected in series to a first capacitor.

3. An asymmetrical duty cycle flyback converter as set forth in claim 2, wherein said rectifying/smoothing means includes:

a diode having its anode connected to one side of said secondary winding of said main transformer; and

a second capacitor connected between the other side of said secondary winding of said main transformer and a cathode of said diode.

4. An asymmetrical duty cycle flyback converter as set forth in claim 1, wherein said first delay means includes:

a resistor having its one side connected to an output terminal of said control means;

a reverse diode connected in parallel to said resistor; and

a capacitor having its one side connected to a node between the other side of said resistor and said reverse diode and its other side connected to said ground voltage source.

5. An asymmetrical duty cycle flyback converter as set forth in claim 1, wherein said first comparison means includes a comparator having its non-inverting input terminal (+) connected to an output terminal of said first delay means and its inverting input terminal (-) connected to a first reference voltage source for generating said first reference voltage, said first reference voltage source being connected between said inverting input terminal (-) of said comparator and said ground voltage source.

6. An asymmetrical duty cycle flyback converter as set forth in claim 1, wherein said first buffering means includes npn and pnp transistors connected in series between a supply voltage source and said ground voltage source, said npn and pnp transistors having their bases connected in common to an output terminal of said first comparison means.

7. An asymmetrical duty cycle flyback converter as set forth in claim 1, wherein said electric isolation means includes a transformer with primary and secondary windings, said primary winding of said transformer having its one side connected to an output terminal of said first buffering means through a resistor and a capacitor and its other side connected to said ground voltage source, said secondary winding of said transformer being connected between said gate and a source of said first field effect transistor in said switching means.

8. An asymmetrical duty cycle flyback converter as set forth in claim 1, wherein said second delay means includes:

a resistor having its one side connected to an output terminal of said control means;

a forward diode connected in parallel to said resistor; and

a capacitor having its one side connected to a node between the other side of said resistor and said forward diode and its other side connected to said ground voltage source.

9. An asymmetrical duty cycle flyback converter as set forth in claim 1, wherein said second comparison means includes a comparator having its inverting input terminal (-) connected to an output terminal of said second delay means and its non-inverting input terminal (+) connected to a second reference voltage source for generating said second reference voltage, said second reference voltage source being connected between said non-inverting input terminal (+) of said comparator and said ground voltage source.

10. An asymmetrical duty cycle flyback converter as set forth in claim 1, wherein said second buffering means includes npn and pnp transistors connected in series between a supply voltage source and said ground voltage source, said npn and pnp transistors having their bases connected in common to an output terminal of said second comparison means and their emitters connected in common to said gate of said second field effect transistor in said switching means.