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Asymmetrical duty cycle flyback converter

  • US 5,959,850 A
  • Filed: 11/16/1998
  • Issued: 09/28/1999
  • Est. Priority Date: 11/18/1997
  • Status: Expired due to Fees
First Claim
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1. An asymmetrical duty cycle flyback converter comprising:

  • a main transformer for transforming an input voltage at a desired ratio, said main transformer including a primary winding connected to an input stare and a secondary winding connected to an output stage;

    switching means for switching said input voltage to said main transformer, said switching means including first and second switches;

    rectifying/smoothing means for rectifying and smoothing an output voltage from said main transformer;

    control means for generating a control signal in response to an output voltage from said rectifying/smoothing means to control the switching operation of said switching means; and

    switch driving means for generating first and second drive signals in response to said control signal from said control means to drive said first and second switches in said switching means in such a manner that they can be switched complementarily on the basis of on-time duties asymmetrical with respect to each other and at an interval of a dead time therebetween to perform a zero voltage switching operation,wherein said first and second switches in said switching means include, respectively, first and second field effect transistors connected in series between said input stage and a around voltage source, andwherein said switch driving means includes;

    first delay means for delaying said control signal from said control means for a first predetermined time period;

    first comparison means for comparing the level of an output signal from said first delay means with that of a first reference voltage signal and providing its output signal only when said output signal from said first delay means is higher in level than said first reference voltage signal;

    first buffering means for buffering said output signal from said first comparison means and applying the buffered signal to a gate of said first field effect transistor in said switching means;

    electric isolation means for electrically isolating said first field effect transistor from an output signal from said first buffering means;

    second delay means for delaying said control signal from said control means for a second predetermined time period;

    second comparison means for comparing the level of an output signal from said second delay means with that of a second reference voltage signal and providing its output signal only when said output signal from said second delay means is lower in level than said second reference voltage signal; and

    second buffering means for buffering said output signal from said second comparison means and applying the buffered signal to a gate of said second field effect transistor in said switching means.

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