Programmable analog array circuit

• US 5,959,871 A
• Filed: 12/22/1994
• Issued: 09/28/1999
• Est. Priority Date: 12/23/1993
• Status: Expired due to Fees

• Current Assignee: State Of Oregon Acting By And Through The State Board Of Higher Education On Behalf Of Portland State University
• Original Assignee: Analogix/Portland State University
• Inventors: Perkowski, Marek A., Pierzchala, Edmund
• Primary Examiner(s): Trans, Vincent N.
• Application Number:
  US08/362,838
• Time in Patent Office: 1,741 Days
• Field of Search: 364/488, 364/489, 364/490, 326/39, 326/41, 327/341, 327/526, 327/566, 327/565
• US Class Current: 703/4
• CPC Class Codes: G06G 7/06 Programming arrangements, e.g. plugboard for interconnecting functional units of the computer; Digital programming hybrid computers G06J

Abstract

There is disclosed a programmable analog or mixed analog/digital circuit. More particularly, this invention provides a circuit architecture that is flexible for a programmable electronic hardware device or for an analog circuit whose input and output signals are analog or multi-valued in nature, and primarily continuous in time. There is further disclosed a design for a current-mode integrator and sample-and-hold circuit, based upon Miller effect.

Claims

1. A programmable analog device comprising an array of programmable analog signal processing cells, wherein each analog signal processing cell comprises an analog signal processing portion and a control circuit, wherein the control circuit controls the operation of the analog signal processing portion and may also take part in auxiliary information processing, wherein the array of programmable analog signal processing cells are locally interconnected by one or a plurality of signal interconnections to form the programmable analog device, wherein a cell is considered locally interconnected in that the number of cells connected to a given cell by programmable analog signal connections connected to the cell does not change as the number of cells in the programmable analog device varies, whereby a total length of unprogrammed signal connections has been minimized.

2. The programmable analog device of claim 1, further comprising one or a plurality of signal interconnections for connecting various cells of the array together, wherein said signal interconnections result in some cells becoming globally connected, wherein a cell is considered globally interconnected in that the number of cells connected to a given cell by programmable analog signal connections connected to the cell changes as the number of cells in the array varies, whereby a total length of unprogrammed signal connections has been minimized.

3. The programmable analog device of claim 2 wherein the control circuit comprises a means for exchanging information to and from the control circuit, a means for storing information, or a means for communicating with an associated analog processing portion of a cell.

4. The programmable analog device of claim 3 wherein the control circuit is programmed to determine the operation of the analog processing portion of the cell, and the analog processing portion of a cell comprises a means for performing one or more mathematical and other functions.

5. The programmable analog device of claim 4 wherein the analog processing portion is programmed by changing the operating point (bias) of electron devices in the signal path and not by using switches in the signal path.

6. The programmable analog device of claim 5 wherein the analog processing portion comprises an amplifier/integrator, wherein the amplifier/integrator comprises an operational transconductance amplifier (OTA) input stage, having an input signal and an output signal connected to a current amplifier, wherein the current amplifier comprises an additional voltage mode output, and a capacitor or a plurality of capacitors connected to the voltage mode output of the current amplifier and to the input of the OTA, wherein the current-mode output signal of the amplifier is proportional to its voltage-mode output signal, which represents the integral of the input current-mode signal, wherein the amplifier/integrator further optionally comprises an input current buffer having a current-mode input and two current-mode outputs, whereby one output is connected to the input of the OTA and the other output is connected to the input of the amplifier/integrator.