Ferroelectric memory cell with shunted ferroelectric capacitor and method of making same

• US 5,959,878 A
• Filed: 09/15/1997
• Issued: 09/28/1999
• Est. Priority Date: 09/15/1997
• Status: Expired due to Fees

• Current Assignee: Celis Semiconductor Corp.
• Original Assignee: Celis Semiconductor Corp.
• Inventors: Kamp, David A.
• Primary Examiner(s): Nguyen, Viet Q.
• Application Number:
  US08/931,023
• Time in Patent Office: 743 Days
• Field of Search: 365/117, 365/145, 365/189.01, 365/203
• US Class Current: 365/117
• CPC Class Codes: G11C 11/22 using ferroelectric elements
• CPC Class Codes: H10B 53/00 Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors

Abstract

A ferroelectric memory includes a transistor having a source/drain, a capacitor having a first electrode and a second electrode, and a plate line connected to the second electrode. The first electrode is connected to the source/drain of the transistor to create a node that is isolated when the transistor is off. A shunt system directly electrically connects the isolated node and the second electrode of said capacitor at a predetermined time to essentially equalize the voltages on the first and second electrodes of said capacitor during the predetermined time. In different embodiments the shunt is a Schottky diode, a resistor, and a pair of back-to-back diodes and a transistor. In the embodiment in which the shunt is a transistor, the shunt line connected to the shunt transistor gate is boosted, there is a shunt transistor connecting each isolated node in a portion of the memory, to the adjacent isolated node, and every eight to thirty-two isolated nodes, another shunt transistor connects the chain of isolated nodes to the plate line.

Claims

1. A ferroelectric memory comprising:

a transistor having a source/drain;

a capacitor having a first electrode and a second electrode, said first electrode connected to said source/drain of said transistor to create a node that is isolated when said transistor is off; and

a shunt system for directly electrically connecting said isolated node and said second electrode of said capacitor at a predetermined time to essentially equalize the voltages on said first and second electrodes of said capacitor during said predetermined time;

wherein said memory includes a plurality of memory cells, each of said memory cells including one of said isolated nodes, and said shunt system comprises;

a first shunt device for directly electrically connecting said one of said isolated nodes in each of said cells to one of said isolated nodes in another of one of said cells during said predetermined time; and

a second shunt device for directly electrically connecting at least one of said isolated nodes to said second electrode of said capacitor during said predetermined time.

2. A ferroelectric memory as in claim 1 wherein said shunt system comprises a shunt device selected from the group consisting of:

a Schottky diode, a resistor, and a pair of back-to-back diodes.

3. A ferroelectric memory as in claim 1 wherein said shunt system comprises a shunt transistor.

4. A ferroelectric memory as in claim 3 wherein said memory includes a supply voltage power source having an output voltage, said shunt transistor includes a gate, and said shunt system includes:

a shunt line connected to the gate of said shunt transistor; and

a signal generator for applying a shunt line signal to said shunt line, which signal is boosted above the voltage of said output voltage for at least a portion of said predetermined time.

5. A ferroelectric memory as in claim 1 wherein there is one of said second shunt devices for every 2ⁿ of said memory cells, where n is an integer from zero to 10.

6. A ferroelectric memory as in claim 1 wherein there is one of said second shunt devices for every eight to thirty-two of said memory cells.

7. A ferroelectric memory as in claim 1 wherein said memory further comprises a plate line for providing a voltage signal to said second electrode of said capacitor, and said shunt system comprises a shunt device for directly electrically connecting said isolated node and plate line.

8. A ferroelectric memory as in claim 1 wherein said memory includes a memory cell having two of said transistors, two of said capacitors, and two of said isolated nodes, and said shunt system comprises a shunt device for directly electrically connecting said two isolated nodes.

9. A ferroelectric memory as in claim 1 wherein said transistor and capacitor are part of a first memory cell in said memory, said memory includes a plurality of said memory cells and a plurality of word lines connected to the gates of the transistors in said memory cells, and said predetermined time includes essentially all of the cycles of said memory in which the word line connected to said first memory cell is not selected.

10. A ferroelectric memory cell comprising:

a transistor having a source/drain;

a capacitor having a first electrode and a second electrode, said first electrode connected to said source/drain of said transistor to create a node that is isolated when said transistor is off; and

a shunt device for directly electrically connecting said isolated node and said second electrode of said capacitor at a predetermined time to essentially equalize the voltages on said first and second electrodes of said capacitor at said predetermined time, said shunt device selected from the group consisting of;

a Schottky diode and a pair of back-to-back diodes.

11. A method of operating a ferroelectric memory including:

a bit line, a word line, and a plate line;

a memory cell comprising a transistor having a first source/drain, a second source/drain, and a gate; and

a capacitor having a first electrode and a second electrode, with said first electrode connected to said first source/drain of said transistor to create a node that is isolated when said transistor is off;

wherein said bit line is connected to said second source drain, said word line is connected to said gate, and said plate line is connected to said second electrode;

said method comprising the steps of;

directly electrically connecting said isolated node and said second electrode of said capacitor at a predetermined time to essentially equalize the voltages on said first and second electrodes of said capacitor at said predetermined time;

performing a write/rewrite cycle on said memory cell, including the step of raising the voltage on said word line; and

at the end of said write/rewrite cycle, adjusting the voltage on said bit line to the same voltage as the voltage on said plate line.

12. A method as in claim 11 wherein said memory includes a bit line, a word line, and a plate line, said transistor includes a second source/drain and a gate, said bit line is connected to said second source drain, said word line is connected to said gate, and said plate line is connected to said second electrode, and said method further comprises:

performing a write/rewrite cycle on said memory cell, including the step of raising the voltage on said word line; and

at the end of said write/rewrite cycle, adjusting the voltage on said bit line to the same voltage as the voltage on said plate line.

13. A method of manufacturing a ferroelectric memory comprising a transistor having a gate and source/drain, a word line connected to said gate, a capacitor having a first electrode and a second electrode with said first electrode connected to said source/drain of said transistor to create a node that is isolated when said transistor is off, and a shunt for directly electrically connecting said second electrode and said isolated node, said method comprising the steps of:

fabricating a word line by forming a conductive layer and patterning said conductive layer; and

at the same time and in the same process steps as said step of fabricating said word line, fabricating said shunt line.

14. A method of manufacturing as in claim 13 and further including the steps of:

fabricating a connector between said first electrode and said source/drain; and

at the same time and in the same process steps as said step of fabricating a connector, fabricating a connector between said node and said second electrode.

15. A ferroelectric memory comprising:

a supply voltage power source having an output voltage;

a transistor having a source/drain and a gate;

a capacitor having a first electrode and a second electrode, said first electrode connected to said source/drain of said transistor to create a node that is isolated when said transistor is off;

a shunt system for directly electrically connecting said isolated node and said second electrode of said capacitor at a predetermined time to essentially equalize the voltages on said first and second electrodes of said capacitor during said predetermined time; and

said shunt system further includes;

a shunt line connected to the gate of said shunt transistor; and

a signal generator for applying a shunt line signal to said shunt line, which signal is boosted above the voltage of said output voltage for at least a portion of said predetermined time.

16. A ferroelectric memory comprising:

a transistor having a source/drain;

a capacitor having a first electrode and a second electrode, said first electrode connected to said source/drain of said transistor to create a node that is isolated when said transistor is off; and

a shunt system for directly electrically connecting said isolated node and said second electrode of said capacitor at a predetermined time to essentially equalize the voltages on said first and second electrodes of said capacitor during said predetermined time;

wherein said memory includes a memory cell having two of said transistors, two of said capacitors, and two of said isolated nodes, and said shunt system comprises a shunt device for directly electrically connecting said two isolated nodes.

17. A method of operating a ferroelectric memory including;

a supply voltage power source having an output voltage;

a shunt transistor including a gate;

a shunt line connected to the gate of said shunt transistor; and

a memory cell comprising a transistor having a first source/drain and a capacitor having a first electrode and a second electrode, with said first electrode connected to said source/drain of said transistor to create a node that is isolated when said transistor is off, said method comprising the step of;

directly electrically connecting said isolated node and said second electrode of said capacitor via said shunt transistor by applying, at a predetermined time, a voltage to said shunt line that is higher than said output voltage to essentially equalize the voltages on said first and second electrodes of said capacitor at said predetermined time.

18. A method of operating a ferroelectric memory including a memory cell comprising a transistor having a first source/drain and a capacitor having a first electrode and a second electrode, with said first electrode connected to said source/drain of said transistor to create a node that is isolated when said transistor is off, said memory cell including two of said transistors, two of said capacitors, and two of said isolated nodes, said method comprising the steps of:

directly electrically connecting each of said isolated nodes to the second electrode of the corresponding capacitor at a predetermined time; and

directly electrically connecting said isolated nodes at said predetermined time;

to essentially equalize the voltages on said first and second electrodes of said capacitor at said predetermined time.