Programmable logic device including configuration data or user data memory slices

• US 5,959,881 A
• Filed: 12/30/1997
• Issued: 09/28/1999
• Est. Priority Date: 08/18/1995
• Status: Expired due to Term

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Wong, Jennifer, Trimberger, Stephen M., Carberry, Richard A., Johnson, Robert Anders
• Primary Examiner(s): Fears, Terrell W.
• Application Number:
  US09/001,156
• Time in Patent Office: 637 Days
• Field of Search: 365/51, 365/182, 365/63, 365/189.01, 365/230.01
• US Class Current: 365/182
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: H03K 19/17752 for hot reconfiguration
• CPC Class Codes: H03K 19/17756 for partial configuration or partial reconfiguration
• CPC Class Codes: H03K 19/17758 for speeding up configuration or reconfiguration
• CPC Class Codes: H03K 19/1776 for memories

Abstract

A programmable logic device (PLD) comprises at least one configurable element, and a plurality of programmable logic elements for configuring the configurable element(s). Alternatively, a PLD comprises an interconnect structure and a plurality of programmable logic elements for configuring the interconnect structure. In either embodiment, at least one of the programmable logic elements includes N memory cells. A predetermined one of the N memory cells forms part of a memory slice, wherein at least a portion of each slice of the programmable logic device is allocated to either configuration data or user data memory. Typically, one memory slice provides one configuration of the programmable logic device. In accordance with one embodiment, a memory access port is coupled between at least one of the N memory cells and either one configurable element or the interconnect, thereby facilitating loading of new configuration data into other memory slices during the one configuration. The new configuration data may include off-chip or on-chip data. The present invention typically allocates at least one slice to user data memory and includes means for disabling access to at least one of the N memory cells.

Claims

1. A programmable logic device comprising:

at least one configurable element;

a plurality of programmable logic elements for configuring said at least one configurable element, wherein at least one of said programmable logic elements includes N memory cells, wherein a predetermined one of said N memory cells for said plurality of programmable logic elements forms part of a memory slice, wherein one memory slice provides one configuration of said programmable logic device, and wherein at least a portion of each slice of said programmable logic device is allocated to either configuration data or user data memory; and

means for loading new user data into other memory slices during said one configuration.

2. The programmable logic device of claim 1 further including a storage device for storing a plurality of intermediate states of one configurable element.

3. The programmable logic device of claim 1 wherein said new user data includes off-chip data.

4. A programmable logic device comprising:

at least one configurable element;

a plurality of programmable logic elements for configuring said at least one configurable element, wherein at least one of said programmable logic elements includes N memory cells, wherein a predetermined one of said N memory cells for said plurality of programmable logic elements forms part of a memory slice and further wherein one memory slice provides one configuration of said programmable logic device;

a memory storage element coupled between at least one of said N memory cells and one configurable element; and

means for loading new user data into other memory slices during said one configuration.

5. The programmable logic device of claim 4 wherein said new user data includes off-chip data.

6. A programmable logic device comprising:

an interconnect structure;

a plurality of programmable logic elements for configuring said interconnect structure, wherein at least one of said programmable logic elements includes N memory cells, wherein a predetermined one of said N memory cells for said plurality of programmable logic elements forms part of a memory slice, wherein one memory slice provides one configuration of said programmable logic device, and wherein at least a portion of each slice of said programmable logic device is allocated to either configuration data or user data memory; and

means for loading new user data into other memory slices during said one configuration.

7. A programmable logic device comprising:

an interconnect structure;

a plurality of programmable logic elements for configuring said interconnect structure, wherein at least one of said programmable logic elements includes N memory cells, wherein a predetermined one of said N memory cells for said plurality of programmable logic elements forms part of a memory slice, and wherein at least a portion of each slice of said programmable logic device is allocated to either configuration data or user data memory, wherein said new user data memory includes off-chip data; and

a memory storage element coupled between at least one of said N memory cells and said interconnect structure.