MPEG decoding system adjusting the presentation in a predetermined manner based on the actual and requested decoding time

• US 5,960,006 A
• Filed: 09/23/1996
• Issued: 09/28/1999
• Est. Priority Date: 09/09/1994
• Status: Expired due to Term

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Neuman, Darren, Auld, David R., Maturi, Greg
• Primary Examiner(s): Kim, Kenneth S.
• Application Number:
  US08/717,843
• Time in Patent Office: 1,100 Days
• Field of Search: 348/512, 348/513, 370/509, 386/65, 395/551, 395/559
• US Class Current: 370/509
• CPC Class Codes: G06T 9/007 Transform coding, e.g. discrete cosine transform
• CPC Class Codes: H04N 21/4305 Synchronising client clock from received content stream, e.g. locking decoder clock with encoder clock, extraction of the PCR packets arrangements for synchronising receiver with transmitter by comparing receiver clock with transmitter clock H04L7/0012; arrangements for synchronising receiver with transmitter wherein the receiver takes measures against momentary loss of synchronisation H04L7/0083
• CPC Class Codes: H04N 21/43072 of multiple content streams on the same device
• CPC Class Codes: H04N 21/44004 involving video buffer management, e.g. video decoder buffer or video display buffer

Abstract

A Motion Picture Experts Group (MPEG) multiplexed data bitstream includes encoded video and audio data units, which are prefixed with headers including Presentation Time Stamps (PTS) indicating desired presentation times for the respective data units. The data units are decoded, and presented at a fixed time after decoding, such that the fixed time can be subtracted from the PTS to provide a desired decoding time. The bitstream is parsed, the video and audio headers are stored in video and audio header memories, and the associated video and audio data units are stored in video and audio channel memories respectively. A first interrupt is generated each time a header is stored, and a host microcontroller responds by storing the PTS from the header and the starting address of the corresponding data unit in the channel memory as an entry in a list. A second interrupt is generated each time a data unit is decoded, and the host microcontroller responds by accessing the list using the starting address of the data unit to obtain the corresponding PTS, and thereby the desired decoding time. Decoding and presentation are synchronized by comparing the desired decoding time with a system clock time. If the desired decoding time is later than the system clock time by more than one presentation (frame) time period for the data unit, presentation of the data unit is skipped. If the desired decoding time is earlier than the system clock time by more than the presentation time period, presentation of the data unit is repeated.

Claims

1. A system for decoding a data stream, said data stream comprising an encoded data unit, a header corresponding to said encoded data unit, and a time stamp in said header for indicating a requested decoding time for said encoded data unit, comprising:

a header memory;

a data memory;

a list memory;

a parser adapted to parse said data stream, store said header in the header memory, store said encoded data unit in the data memory beginning at a starting address and capture said time stamp;

a decoder adapted to read and decode said encoded data unit from the data memory at an actual decoding time to produce a decoded data unit; and

a storage unit adapted to store the time stamp in a list entry in said list memory, said storage unit being responsive to said decoder to access, while said encoded data unit is being decoded by said decoder, said list entry using said starting address to obtain said time stamp;

wherein the relationship between said requested decoding time and said actual decoding time affects subsequent presentation of said decoded data unit in a predetermined manner.

2. A system as in claim 1, wherein said actual decoding time can differ from said requested decoding time.

3. A system as in claim 1, wherein the relationship between said requested decoding time and said actual decoding time can be utilized to synchronize subsequent presentation of said decoded data unit.

4. A system as in claim 1, further comprising:

a system timer adapted to maintain a system clock time; and

a comparator adapted to compare said time stamp with a current value of said system clock time from the system timer when the decoder begins to read and decode said encoded date unit.

5. A system as in claim 4, wherein the difference between the time stamp and the current value of the system clock time constitutes said actual decoding time.

6. A system as in claim 4, further comprising:

a presentation unit adapted to present said decoded data unit; and

a synchronizer adapted to control said presentation unit to repeat presentation of said decoded data unit if said time stamp exceeds said current value of said system clock time by more than a first predetermined value; and

to control said presentation unit to skip presentation of said decoded data unit if said current value of said system clock time exceeds said time stamp by more than a second predetermined value.

7. A system as in claim 6, wherein:

the presentation unit begins to present said decoded data unit at a predetermined time interval after the decoder begins to decode said encoded data unit;

said time stamp indicates said presentation time directly, thereby indicating said decoding time indirectly as being equal to the difference between said presentation time and said predetermined time interval; and

the synchronizer determines said decoding time by subtracting said predetermined time interval from said time stamp.

8. A system as in claim 7, wherein:

said data stream is an MPEG bitstream; and

said time stamp is a presentation time stamp.

9. A system as in claim 6, wherein said first predetermined value is equal to said second predetermined value.

10. A system as in claim 9, wherein:

said decoded data unit is a video frame; and

said first and second predetermined values are substantially equal to a frame presentation rate.

11. A system in claim 1, wherein:

said data memory comprises a circular buffer; and

said parser is adapted to append a value indicating a number of times said circular buffer has rolled over to the starting address for storing in the list memory.

12. A system as in claim 11, wherein:

said starting address is a binary number; and

said parser is adapted to append said value to said binary number as a predetermined number of most significant bits.

13. A system as in claim 1, wherein said data stream further comprises a system time stamp, and the system further comprises:

a system timer adapted to maintain a system clock time;

a comparator adapted to compare said system time stamp to a current value of said system clock time; and

a synchronizer adapted to adjust the system timer means such that said current value of said system clock time becomes substantially equal to said system time stamp.

14. A system as in claim 13, wherein the synchronizer adjusts the system timer by resetting said system clock time to a value based on said system time stamp.

15. A system as in claim 13, wherein:

the system timer comprises;

a clock pulse generator; and

a counter that clocked by the clock pulse generator such that said system clock time comprises a count of the counter; and

the synchronizer adjusts the system timer by altering a frequency of the clock pulse generator.

16. A system as in claim 1, wherein:

said storage unit is adapted to store said time stamp and said starting address as a list entry in said list memory;

said parser generates a first interrupt upon storing said header in said header memory;

said storage unit stores aid time stamp and said starting address as a list entry in said list memory in response to said first interrupt;

said decoder generates a second interrupt upon beginning of reading and decoding said encoded data unit at said actual decoding time; and

said storage unit accesses said list entry in the list memory using said starting address to obtain said time stamp in response to said second interrupt.

17. A decoder for decoding a data stream, said data stream comprising an encoded data unit, and a header corresponding to said encoded data unit, said header including a time stamp indicating a requested decoding time for said encoded data unit, comprising:

a header memory adapted to store said header;

a data memory adapted to store said encoded data unit;

a list memory;

a parser which parses said data stream, stores said header in said header memory, stores said encoded data unit in said data memory at a starting address, appends said starting address to said header stored in said header memory, and generates a first interrupt;

a microcontroller which responds to said first interrupt by extracting said time stamp and said starting address from said header, and storing said time stamp and said starting address as a list entry in said list memory;

a decoder which reads and decodes said encoded data unit from said data memory to produce a decoded data unit at an actual decoding time, and generates a second interrupt prior to decoding said encoded data unit;

said microcontroller responding to said second interrupt by accessing said list entry using said starting address to obtain said time stamp; and

said actual decoding time and said time stamp being used to synchronize subsequent presentation of said decoded data unit.

18. A decoder as in claim 17, further comprising:

a system timer adapted to maintain a system clock time.

19. A decoder as in claim 18, further comprising:

a presentation unit adapted to present said decoded data unit; and

a synchronizer adapted to control said presentation unit to repeat presentation of said decoded data unit under said first predetermined condition and to control said presentation unit to skip presentation of said decoded data unit under said second predetermined condition.

20. A decoder as in claim 19, wherein said first predetermined condition comprises said time stamp exceeding said current value of said system clock time by more than a first predetermined value and said second predetermined condition comprises said current value of said system clock time exceeding said time stamp by more than a second predetermined value.

21. A decoder as in claim 20, wherein:

the presentation unit begins to present said decoded data unit at a predetermined time interval after said reader/decoder begins to decode said encoded data unit;

said time stamp indicates said presentation time directly, and thereby indicates said decoding time indirectly as being equal to said presentation time minus said predetermined time interval; and

the synchronizer determines said decoding time by subtracting said predetermined time interval from said time stamp.

22. A decoder as in claim 21, wherein:

said data stream is an MPEG bitstream; and

said time stamp is a presentation time stamp.

23. A decoder as in claim 20, wherein said first predetermined value is equal to said second predetermined value.

24. A decoder as in claim 23, wherein:

said decoded data unit is a video frame; and

said first and second predetermined values are substantially equal to a frame presentation rate.

25. A decoder as in claim 18, wherein:

said data stream further comprises a system time stamp; and

said reader/decoder further comprises;

a system timer adapted to maintain a system clock time;

a comparator adapted to compare said system time stamp to a current value of said system time; and

a synchronizer adapted to adjust said system timer such that said current value of said system clock time becomes substantially equal to said system time stamp.

26. A decoder as in claim 25, wherein said synchronizer adjusts said system timer by resetting said system clock time to a value based on said system time stamp.

27. A decoder as in claim 26, wherein the system timer comprises:

a clock pulse generator; and

a counter that is clocked by the clock pulse generator such that said system clock time comprises a count of the counter; and

the synchronizer adjusts the system timer by altering a frequency of the clock pulse generator.

28. A method of decoding a data stream, the data stream comprising an encoded data unit, a header corresponding to said encoded data unit, and a time stamp included in said header for indicating a requested decoding time for said encoded data unit, the method comprising the steps of:

(a) parsing said data stream;

(b) storing said header;

(c) storing said encoded data unit beginning at a starting address;

(d) capturing said time stamp;

(e) storing said time stamp and said starting address as a list entry;

(f) reading and decoding said encoded data unit at an actual decoding time to produce a decoded data unit; and

(g) accessing said list entry using said starting address to obtain said time stamp;

wherein the relationship between said requested decoding time and said actual decoding time effects subsequent presentation of said decoding data unit in a predetermined manner.

29. A method as in claim 28, wherein said actual decoding time can differ from said requested decoding time.

30. A method as in claim 28, further comprising the steps of:

(h) maintaining a system time; and

(i) comparing said time stamp with a current value of said system clock time which constitutes said actual decoding time from the system timer means upon performing step (f).

31. A method as in claim 30, further comprising the steps of:

(j) repeating presentation of said decoded data unit if said time stamp exceeds said current value of said system clock time by more than a first predetermined value; and

(k) skipping presentation of said decoded data unit if said current value of said system clock time exceeds said time stamp by more than a second predetermined value.

32. A method as in claim 28, wherein:

step (b) further comprises generating a first interrupt;

step (e) comprises storing said time stamp and said starting address as a list entry in response to said first interrupt;

step (f) comprises generating a second interrupt upon beginning of reading and decoding said encoded data unit; and

step (g) comprises accessing said list entry using said starting address to obtain said time stamp in response to said second interrupt.

33. A decoder for decoding a data stream, said data stream comprising an encoded data unit, and a header corresponding to said encoded data unit, said header including a time stamp indicating a requested decoding time for said encoded data unit, comprising:

a header memory adapted to store said header;

a data memory adapted to store said encoded data unit;

a list memory;

a parser which parses said data stream, stores said header in said header memory, stores said encoded data unit in said data memory at a starting address, appends said starting address to said header stored in said header memory, and generates a first interrupt;

a microcontroller which responds to said first interrupt by extracting said time stamp and said starting address from said header, and stores said time stamp and said starting address as a list entry in said list memory;

a decoder which reads and decodes said encoded data unit from said data memory to produce a decoded data unit, and generates a second interrupt prior to decoding said encoded data unit;

a system timer which maintains a system clock time; and

said microcontroller responding to said second interrupt, while said decoder continues decoding said encoded data unit, by accessing said list entry using said starting address to obtain said time stamp, by capturing said system clock time, and by comparing said time stamp with said captured system clock time to synchronize the presentation of said decoded data unit.

34. A decoder for decoding a data stream, said data stream comprising an encoded data unit, and a header corresponding to said encoded data unit, said header including a time stamp indicating a requested decoding time for said encoded data unit, comprising:

a header memory adapted to store said header;

a data memory adapted to store said encoded data unit;

a list memory;

a parser which parses said data stream, stores said header in said header memory, stores said encoded data unit in said data memory at a starting address, appends said starting address to said header stored in said header memory, and generates a first interrupt;

a microcontroller which responds to said first interrupt by extracting said time stamp and said starting address from said header, and stores said time stamp and said starting address as a list entry in said list memory;

a decoder which reads and decodes said encoded data unit from said data memory to produce a decoded data unit, and generates a second interrupt prior to decoding said encoded data unit;

a system timer which maintains a system clock time;

said microcontroller responding to said second interrupt, while said decoder continues decoding said encoded data unit, by accessing said list entry using said starting address to obtain said time stamp, and by capturing said system clock time; and

a comparator which compares said time stamp with said captured system clock time to synchronize subsequent presentation of said decoded data unit.