Matched filter

• US 5,960,033 A
• Filed: 04/02/1997
• Issued: 09/28/1999
• Est. Priority Date: 04/02/1996
• Status: Expired due to Fees

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Shibano, Toshinobu, Iizuka, Kunihiko
• Primary Examiner(s): Le, Amanda
• Application Number:
  US08/825,864
• Time in Patent Office: 909 Days
• Field of Search: 375/207, 375/200, 375/343, 364/724.011, 364/724.11, 327/551
• US Class Current: 375/152
• CPC Class Codes: H03H 17/0254 Matched filters
• CPC Class Codes: H04B 1/7093 Matched filter type
• CPC Class Codes: H04B 2201/70703 using multiple or variable rates

Abstract

A sample-hold circuit, which is constituted by a capacitor and a differential amplifier or a capacitor and an inversion amplifier, is provided with a first switch for short-circuiting the input and output, a second switch for switching the input-side terminal of the input capacitor to a reference voltage input, a third switch for switching the output-side terminal of the feedback capacitor to the reference voltage input, and a fourth switch for switching the input-side terminal of the input capacitor to an input voltage; thus a refreshing operation is available. Consequently, it is possible to compensate for deviations in offset voltage that are inherently caused by process deviations of MOS amplifiers, and to improve the precision of the output of the matched filter. Moreover, in addition to sample-hold circuits having conventional number of steps, a plurality of sample-hold circuits are added, and steps of shift registers, which have binary correlation filter coefficients stored therein, are also added as many as the same number of the added sample-hold circuits. Thus, during the refreshing operation, the extra circuits are used to carry out the process. With this arrangement, it becomes possible to provide a matched filter that is capable of refreshing the sample-hold circuits without adversely affecting the correlation output.

Claims

1. A matched filter, which, each time a predetermined input clock is inputted thereto, carries out correlation operations between an analog signal and correlation filter coefficients the number of which is not more than a predetermined maximum length, comprising:

sample-hold circuits of a capacitive-coupling type, which are placed in parallel with each other with the number being at least more than the maximum length, which hold sampled values of the inputted analog signal during the time in which the input clocks are applied at least as many as the number of the correlation filter coefficients, and which have refresh sections for setting an operational reference electric potential respectively;

a correlation filter coefficient register which is constituted by first registers that are installed in association with the sample-hold circuits and which allows first register values to cyclicly shift step by step for each input clock, the first register values being stored in the respective first registers, and representing the correlation efficiencies that are to be combined with the corresponding sample-hold circuits at the cycle of the input clock;

an operation means for carrying out correlation operations based upon the combinations of the first register values of the correlation filter coefficient register and the outputs of the corresponding sample-hold circuits; and

sample-hold control means which are installed as many as the number of the steps of the sample-hold circuits in a cyclic manner and which, upon releasing to the corresponding sample-hold circuit a control signal indicating one of sampling, refreshing and holding states, outputs the control signal having the same contents as the control signal at the previous step in the cycle of the input clock took place immediately before.

2. The matched filter as defined in claim 1, further comprising:

an output-suppressing register which is constituted by second registers that are installed in association with the sample-hold circuits and which allows second register values to cyclicly shift step by step for each input clock, the second register values being stored in the respective second registers, and indicating whether or not the output of the corresponding sample-hold circuit contributes to a correlation operation at the current cycle of the input clock;

multiplexors which are placed between the sample-hold circuits and the operation means and which select either the outputs of the sample-hold circuits or the operational reference electric potential so as to input them to the operation means; and

multiplexor control means which, if the second register value indicates no contribution to the correlation operation, allows the corresponding multiplexor to select the operational reference electric potential.

3. The matched filter as defined in claim 1, wherein each of the sample-hold circuits includes a switch that is installed at an output end of the corresponding sample-hold circuit and that disconnects the output of the sample-hold circuit from the succeeding sample-hold circuit during a period in which the sample-hold control means is outputting a control signal indicating a sampling operation.

4. The matched filter as defined in claim 1, further comprising:

a multiplexor that is placed between the corresponding sample-hold circuit and the operation means and that selects either the output of the sample-hold circuit or the operational reference electric potential, and then inputs the result to the operation means; and

multiplexor control means which, at least during a period in which the sample-hold control means at the corresponding step is outputting a control signal indicating a sampling operation, allows the multiplexor to select the operational reference electric potential, the multiplexor and the multiplexor control means being installed in association with each of the sample-hold circuits.

5. The matched filter as defined in claim 1, further comprising:

a multiplexor that is placed between the corresponding sample-hold circuit and the operation means and that selects either the output of the sample-hold circuit or the operational reference electric potential, and then inputs the result to the operation means; and

multiplexor control means which, at least during a period in which the sample-hold control means at the corresponding step is outputting a control signal indicating a refreshing operation, allows the multiplexor to select the operational reference electric potential, the multiplexor and the multiplexor control means being installed in association with each of the sample-hold circuits.

6. The matched filter as defined in claim 5, wherein each of the multiplexor control means allows the multiplexor at the corresponding step to select the operational reference electric potential also during a period in which the sample-hold control means at the corresponding step is outputting a control signal indicating a sampling operation.

7. The matched filter as defined in claim 1, wherein the operation means comprises:

addition-related and subtraction-related product-operation multiplexors that select and output either the output of the corresponding sample-hold circuit or the operational reference electric potential; and

multiplexor control means for controlling the addition-related and subtraction-related product-operation multiplexors based upon the first register value of the correlation-filter coefficient register corresponding to the sample-hold circuit in question, the addition-related and subtraction-related multiplexors and the multiplexor control means being installed in association with each of the sample-hold circuits, the operation means further comprising;

an addition-related adder to which the outputs of the addition-related product-operation multiplexor are inputted;

a subtraction-related adder to which the outputs of the subtraction-related product-operation multiplexor are inputted; and

a subtracter that outputs the difference between the outputs of the addition-related and subtraction-related adders as a correlation output.

8. The matched filter as defined in claim 7, wherein each of the multiplexor control means allows the addition-related and subtraction-related multiplexors to select the operational reference electric potential during a period including at least the period in which the sample-hold control means at the corresponding step is outputting the control signal indicating the sampling operation and the period in which the sample-hold control means is outputting the control signal indicating the refreshing operation.

9. The matched filter as defined in claim 7, wherein:

the addition-related and subtraction-related adders are adders of a capacitive-coupling type, each having an adder refresh section; and

two systems, each including the addition-related and subtraction-related product-operation multiplexors, the addition-related and subtraction-related adders and the subtracter, are provided, the matched filter further comprising;

an output multiplexor for selecting and outputting one of the outputs of the subtracters of the two systems; and

switching means which instructs the addition-related and subtraction-related adders and the subtracter of the system that has been selected by the output multiplexor to carry out a computing operation, as well as instructing the adder refresh section of the other system to carry out a refreshing operation.

10. The matched filter as defined in claim 1, wherein each of the refresh section sets the input of the corresponding sample-hold circuit at the operational reference electric potential after the refreshing operation.

11. The matched filter as defined in claim 1, wherein:

each of the sample-hold circuits includes an amplifier for amplifying the inputs, an input capacitor having one end connected to the input of the amplifier, and a feedback capacitor that is placed between the input of the amplifier and the output of the corresponding sample-hold circuit; and

the refresh section of the corresponding sample-hold circuit includes a first switch for short-circuiting and disconnecting the input and output of the amplifier, and a second switch that selects either the analog signal or the operational reference electric potential and applies it to the end of the input capacitor on the side opposite to the amplifier.

12. The matched filter as defined in claim 11, wherein each of the refresh sections further includes a third switch that selects either the operational reference electric potential or the output voltage of the amplifier and applies it to the end of the feedback capacitor on the output side.

13. The matched filter as defined in claim 11, wherein the number of the sample-hold circuits is set to be greater than the maximum length by one.

14. The matched filter as defined in claim 12, wherein supposing that the number of the sample-hold circuits is α

, the maximum length is m, and the length of a period in which the second and third switches are selecting the operational reference electric potential side is represented by n cycles of the input clock, n being a natural number, the following equation is satisfied;

space="preserve" listing-type="equation">α

=m+n+3.

15. The matched filter as defined in claim 14, wherein each of the sample-hold control means, upon instructing refresh and sampling operations to the corresponding sample-hold circuit, allows the first switch to conduct during the n cycles of the input clock, allows the second and third switches to select the operational reference electric potential side during a period of conduction of the first switch as well as during a period of one cycle of the input clock immediately after said period, and outputs a control signal indicating a sampling operation after one cycle of the input clock has elapsed since the second and third switches selected the side that is different from the operational reference electric potential side.

17. The matched filter as defined in claim 1, which is used for synchronism acquisition of a receiving signal of a spectrum spread communication system.

16. A matched filter, which, each time a predetermined input clock is inputted thereto, carries out correlation operations between an analog signal and correlation filter coefficients the number of which is not more than a predetermined maximum length, comprising:

sample-hold circuits which are placed in parallel with each other with the number being at least the same as the maximum length and to which the analog signal is inputted;

a correlation filter coefficient register which is constituted by first registers that are installed in association with the sample-hold circuits and which allows first register values to cyclicly shift step by step for each input clock, the first register values indicating the correlation filter coefficients related to the corresponding sample-hold circuits at the current cycle of the input clock;

operation means for carrying out correlation operations based upon the combinations of the first register values of the correlation filter coefficient register and the outputs of the corresponding sample-hold circuits;

an output-suppressing register which is constituted by second registers that are installed in association with the sample-hold circuits and which allows second register values to cyclicly shift step by step for each input clock, the second register values indicating whether or not the output of the corresponding sample-hold circuit contributes to a correlation operation at the current cycle of the input clock;

multiplexors which are placed in association with the sample-hold circuits and which select either the outputs of the sample-hold circuits or the operational reference electric potential so as to input them to the operation means; and

multiplexor control means which, if the second register value indicates no contribution to the correlation operation, allows the corresponding multiplexor to select the operational reference electric potential.

18. A control method of a matched filter that has a predetermined number of sample-hold circuits of a capacitive-coupling type, the sample-hold circuits being capable of sampling and holding an inputted analog signal and performing a refreshing operation and being placed in parallel with each other, and that carries out correlation operations between correlation filter coefficients and the analog signal based upon outputs of the sample-hold circuits and the correlation filter coefficients the number of which is smaller than the predetermined number each time an input clock is applied, the control method comprising:

a sampling step of, supposing that ordinal numbers are allocated to the sample-hold circuits cyclicly, at the time when one cycle of the input clock has elapsed from the time of sampling of the sample-hold circuit with one number before, allowing the corresponding sample-hold circuit to sample the analog signal;

a holding step of holding the value that has been sampled at the sampling step until at least a period obtained by multiplying the input clock cycle by the number of the correlation filter coefficients has elapsed; and

a refreshing step of refreshing the corresponding sample-hold circuit between the holding step and the next sampling step.