Emulation system with time-multiplexed interconnect

• US 5,960,191 A
• Filed: 05/30/1997
• Issued: 09/28/1999
• Est. Priority Date: 05/30/1997
• Status: Expired due to Term

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Quickturn Design Systems Incorporated (Cadence Group)
• Inventors: Bershteyn, Mikhail, Butts, Michael R., Sample, Stephen P., Bauer, Jerry R.
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): Broda, Samuel
• Application Number:
  US08/865,741
• Time in Patent Office: 851 Days
• Field of Search: 364/578, 395/500, 395/376, 326/41
• US Class Current: 703/28
• CPC Class Codes: G01R 31/2853 Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections G01R31/31717 takes precedence; test of chip-to-PCB or lead-to-PCB connections G01R31/66
• CPC Class Codes: G01R 31/31717 Interconnect testing by scan techniques see G01R31/31855
• CPC Class Codes: G06F 30/331 with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
• CPC Class Codes: Y10S 370/916 Multiplexer/demultiplexer

Abstract

A hardware emulation system is disclosed which reduces hardware cost by time-multiplexing multiple design signals onto physical logic chip pins and printed circuit board. The reconfigurable logic system of the present invention comprises a plurality of reprogrammable logic devices, and a plurality of reprogrammable interconnect devices. The logic devices and interconnect devices are interconnected together such that multiple design signals share common I/O pins and circuit board traces. A logic analyzer for a hardware emulation system is also disclosed. The logic circuits necessary for executing logic analyzer functions is programmed into the programmable resources in the logic chips of the emulation system.

Claims

1. An electrically reconfigurable logic assembly for use in an electrically reconfigurable hardware emulation system which can be configured with a circuit design in response to the input of circuit information, said electrically reconfigurable logic assembly comprising:

a plurality of reprogrammable logic devices disposed on a printed circuit board, each of said reprogrammable logic devices having internal circuitry which can be reprogrammably configured to provide functional elements selected from the group of at least combinatorial logic elements and storage elements, each of said reprogrammable logic devices also having programmable input/output terminals which can be reprogrammably connected to selected ones of said functional elements configured into said reprogrammable logic devices, said reprogrammable logic devices also having an input demultiplexer and an output multiplexer implemented at at least one input/output terminal, said input demultiplexer receiving a time-multiplexed signal and dividing said time-multiplexed signal into one or more internal signals, said output multiplexer combining one or more internal signals onto a first single physical interconnection;

a plurality of reprogrammable interconnect devices disposed on said printed circuit board, each of said reprogrammable interconnect devices having input/output terminals and internal circuitry which can be reprogrammably configured to provide interconnections between selected ones of said input/output terminals, said plurality of reprogrammable interconnect devices also having an input demultiplexer and an output multiplexer implemented at at least one input/output terminal, said input demultiplexer receiving a time-multiplexed input signal and dividing it into one or more component signals, said output multiplexer combining said one or more component signals or other component signals onto a second single physical interconnection; and

a set of fixed electrical conductors of said printed circuit board connecting said programmable input/output terminals on said reprogrammable logic devices to said input/output terminals on said reprogrammable interconnect devices such that each of said reprogrammable interconnect devices is connected to at least one but not all of said programmable input/output terminals on each of said reprogrammable logic devices.

2. An electrically reconfigurable logic assembly as recited in claim 1, wherein said reprogrammable logic devices comprise programmable gate arrays.

3. An electrically reconfigurable logic assembly as recited in claim 1, wherein said reprogrammable logic devices comprise field programmable gate arrays.

4. An electrically reconfigurable logic assembly as recited in claim 1, wherein said reprogrammable interconnect devices comprise programmable gate arrays.

5. An electrically reconfigurable logic assembly as recited in claim 1, wherein said reprogrammable interconnect devices comprise field programmable gate arrays.

6. An electrically reconfigurable logic assembly as recited in claim 1, wherein said reprogrammable interconnect devices comprise an integrated circuit having an array of crosspoint switches fabricated thereon.

7. A reprogrammable logic emulation system for implementing a circuit design, the circuit design characterized by a clock path structure and a data path structure, comprising:

a plurality of reprogrammable logic chips disposed on a first circuit board, each of said first plurality of logic chips comprising logic blocks for implementing logical functions and input/output blocks for implementing input/output functions, each of said first plurality of logic chips further comprising a plurality of input/output pins which are programmably electrically connectable to said logic blocks;

a plurality of input demultiplexers implemented in each of said plurality of reprogrammable logic chips, each of said plurality of input demultiplexers electrically communicating with one of said input/output pins on said reprogrammable logic chips;

a plurality of output multiplexers implemented in each of said plurality of reprogrammable logic chips, each of said plurality of output multiplexers electrically communicating with one of said input/output pins on said reprogrammable logic chips;

a plurality of reprogrammable interconnect chips disposed on said first circuit board, each of said reprogrammable interconnect chips having input/output pins and internal circuitry which can be reprogrammably configured to provide interconnections between selected ones of said input/output pins;

a plurality of output multiplexers implemented in each of said plurality of reprogrammable interconnect chips, each of said output multiplexers electrically communicating with one of said input/output pins on said plurality of reprogrammable interconnect chips;

a plurality of input demultiplexers implemented in each of said plurality of reprogrammable interconnect chips, each of said plurality of input demultiplexers electrically communicating with one of said input/output pins on said plurality of reprogrammable logic chips;

a plurality of conductive traces disposed in said first circuit board, each of said plurality of conductive traces electrically connecting one of said input/output pins on one of said reprogrammable logic chips to one of said input/output pins on one of said reprogrammable interconnect chips such that each of said reprogrammable interconnect chips is connected to at least one but not all of said programmable input/output pins on each of said reprogrammable logic chips;

said plurality of output multiplexers implemented in said plurality of reprogrammable logic chips combining one or more internal signals into first time-multiplexed signals;

said plurality of input demultiplexers implemented in said plurality of reprogrammable interconnect chips receiving said first time-multiplexed signals and dividing said first time-multiplexed signals into one or more component signals;

said plurality of output multiplexers implemented in said plurality of reprogrammable interconnect chips combining said one or more component signals into second time-multiplexed signals; and

said plurality of input demultiplexers implemented in said plurality of reprogrammable logic chips receiving said second time-multiplexed signals and dividing said second time-multiplexed signals into one or more internal signals.

8. The reprogrammable logic emulation system of claim 7 wherein said plurality of reprogrammable logic chips comprise field programmable gate arrays.

9. The reprogrammable logic emulation system of claim 7 wherein said plurality of input demultiplexers implemented in each of said plurality of reprogrammable logic chips and said plurality of output multiplexers implemented in each of said plurality of reprogrammable logic chips are implemented using said logic blocks and said input/output blocks of said plurality of reprogrammable logic chips.

10. The reprogrammable logic emulation system of claim 7 wherein each of said time-multiplexed signals is a combination of two design signals.

11. The reprogrammable logic emulation system of claim 7 wherein each of said time-multiplexed signals is a combination of four design signals.

12. A reprogrammable logic emulation system for implementing an integrated circuit design, the integrated circuit design characterized by a clock path structure and a data path structure, comprising:

a plurality of reprogrammable logic chips disposed on a first circuit board, each of said first plurality of logic chips comprising logic blocks for implementing logical functions, said logical functions including both combinational logic functions and sequential logic functions, each of said first plurality of logic chips further comprising a plurality of input/output pins which are programmably electrically connectable to said logic blocks;

a plurality of input demultiplexers implemented in each of said plurality of reprogrammable logic chips, each of said plurality of input demultiplexers electrically communicating with one of said input/output pins on said reprogrammable logic chips;

a plurality of output multiplexers implemented in each of said plurality of reprogrammable logic chips, each of said plurality of output multiplexers electrically communicating with one of said input/output pins on said reprogrammable logic chips;

a plurality of reprogrammable interconnect chips disposed on said first circuit board, each of said reprogrammable interconnect chips having input/output pins and internal circuitry which can be reprogrammably configured to provide interconnections between selected ones of said input/output pins;

a plurality of output multiplexers implemented in each of said plurality of reprogrammable interconnect chips, each of said output multiplexers electrically communicating with one of said input/output pins on said plurality of reprogrammable interconnect chips;

a plurality of input demultiplexers implemented in each of said plurality of reprogrammable interconnect chips, each of said plurality of input demultiplexers electrically communicating with one of said input/output pins on said plurality of reprogrammable logic chips;

a plurality of conductive traces disposed in said first circuit board, each of said plurality of conductive traces electrically connecting one of said input/output pins on one of said reprogrammable logic chips to one of said input/output pins on one of said reprogrammable interconnect chips such that each of said reprogrammable interconnect chips is connected to at least one but not all of said programmable input/output pins on each of said reprogrammable logic chips;

said plurality of output multiplexers implemented in said plurality of reprogrammable logic chips combining one or more signals from said data path structure of said integrated circuit design into first time-multiplexed signals;

said plurality of input demultiplexers implemented in said plurality of reprogrammable interconnect chips receiving said first time-multiplexed signals and dividing said first time-multiplexed signals into one or more component signals;

said plurality of output multiplexers implemented in said plurality of reprogrammable interconnect chips combining said one or more component signals into second time-multiplexed signals; and

said plurality of input demultiplexers implemented in said plurality of reprogrammable logic chips receiving said second time-multiplexed signal and dividing said second time-multiplexed signals into one or more internal signals.

13. The reprogrammable logic emulation system of claim 12 wherein said plurality of reprogrammable logic chips comprise field programmable gate arrays.

14. The reprogrammable logic emulation system of claim 12 wherein said plurality of input demultiplexers implemented in each of said plurality of reprogrammable logic chips and said plurality of output multiplexers implemented in each of said plurality of reprogrammable logic chips implemented using programmable resources of said plurality of reprogrammable logic chips.

15. The reprogrammable logic emulation system of claim 12 wherein each of said time-multiplexed signals is a combination of two design signals.

16. The reprogrammable logic emulation system of claim 12 wherein each of said time-multiplexed signals is a combination of four design signals.

17. An electrically reconfigurable logic assembly for use in an electrically reconfigurable hardware emulation system which can be configured with a circuit design in response to the input of circuit information, said electrically reconfigurable logic assembly comprising:

a plurality of reprogrammable logic devices disposed on a printed circuit board, each of said reprogrammable logic devices having internal circuitry which can be reprogrammably configured to provide functional elements selected from the group of at least combinatorial logic elements and storage elements, each of said reprogrammable logic devices also having programmable input/output terminals which can be reprogrammably connected to selected ones of said functional elements configured into said reprogrammable logic devices, said reprogrammable logic devices also having an input demultiplexer and an output multiplexer implemented at at least one input/output terminal, said input demultiplexer receiving a time-multiplexed signal and dividing said time-multiplexed signal into one or more internal signals, said output multiplexer combining one or more internal signals onto a first single physical interconnection;

a plurality of reprogrammable interconnect devices disposed on said printed circuit board, each of said reprogrammable interconnect devices having input/output terminals and internal circuitry which can be reprogrammably configured to provide interconnections between selected ones of said input/output terminals, said input/output terminals on each of said plurality of reprogrammable interconnect devices receiving a time-multiplexed input and placing said time-multiplexed input on a different one of said input/output terminals; and

a set of fixed electrical conductors connecting said programmable input/output terminals on said reprogrammable logic devices to said input/output terminals on said reprogrammable interconnect devices such that each of said reprogrammable interconnect devices is connected to at least one but not all of said programmable input/output terminals on each of said reprogrammable logic devices.

18. An electrically reconfigurable logic assembly as recited in claim 17, wherein said reprogrammable logic devices comprise programmable gate arrays.

19. An electrically reconfigurable logic assembly as recited in claim 17, wherein said reprogrammable logic devices comprise field programmable gate arrays.

20. An electrically reconfigurable logic assembly as recited in claim 17, wherein said reprogrammable interconnect devices comprise programmable gate arrays.

21. An electrically reconfigurable logic assembly as recited in claim 17, wherein said reprogrammable interconnect devices comprise field programmable gate arrays.

22. An electrically reconfigurable logic assembly as recited in claim 17, wherein said reprogrammable interconnect devices comprise an integrated circuit having an array of crosspoint switches fabricated thereon.

23. A reprogrammable logic emulation system for implementing a circuit design, the circuit design characterized by a clock path structure and a data path structure, comprising:

a plurality of reprogrammable logic chips disposed on a first circuit board, each of said first plurality of logic chips comprising logic blocks for implementing logical functions and input/output blocks for implementing input/output functions, each of said first plurality of logic chips further comprising a plurality of input/output pins which are programmably electrically connectable to said logic blocks;

a plurality of input demultiplexers implemented in each of said plurality of reprogrammable logic chips, each of said plurality of input demultiplexers electrically communicating with one of said input/output pins on said reprogrammable logic chips;

a plurality of output multiplexers implemented in each of said plurality of reprogrammable logic chips, each of said plurality of output multiplexers electrically communicating with one of said input/output pins on said reprogrammable logic chips;

a plurality of reprogrammable interconnect chips disposed on said first circuit board, each of said reprogrammable interconnect chips having input/output pins and internal circuitry which can be reprogrammably configured to provide interconnections between selected ones of said input/output pins;

a plurality of output multiplexers implemented in each of said plurality of reprogrammable interconnect chips, each of said output multiplexers electrically communicating with one of said input/output pins on said plurality of reprogrammable interconnect chips;

a plurality of input demultiplexers implemented in each of said plurality of reprogrammable interconnect chips, each of said plurality of input demultiplexers electrically communicating with one of said input/output pins on said plurality of reprogrammable logic chips;

a plurality of conductive traces disposed in said first circuit board, each of said plurality of conductive traces electrically connecting one of said input/output pins on one of said reprogrammable logic chips to one of said input/output pins on one of said reprogrammable interconnect chips such that each of said reprogrammable interconnect chips is connected to at least one but not all of said programmable input/output pins on each of said reprogrammable logic chips;

said plurality of output multiplexers implemented in said plurality of reprogrammable logic chips combining one or more internal signals into first time-multiplexed signals;

said plurality of input demultiplexers implemented in said plurality of reprogrammable interconnect chips receiving said first time-multiplexed signals and dividing said first time-multiplexed signals into one or more component signals;

said plurality of output multiplexers implemented in said plurality of reprogrammable interconnect chips combining said one or more component signals into second time-multiplexed signals;

said plurality of input demultiplexers implemented in said plurality of reprogrammable logic chips receiving said second time-multiplexed signals and dividing said second time-multiplexed signals into one or more internal signals; and

each of said first time-multiplexed signals and said second time-multiplexed signals are a combination of four design signals.

24. An electrically reconfigurable logic assembly for use in an electrically reconfigurable hardware emulation system which can be configured with a circuit design in response to the input of circuit information, said electrically reconfigurable logic assembly comprising:

a plurality of reprogrammable logic devices disposed on a printed circuit board, each of said reprogrammable logic devices having internal circuitry which can be reprogrammably configured to provide functional elements selected from the group of at least combinatorial logic elements and storage elements, each of said reprogrammable logic devices also having programmable input/output terminals which can be reprogrammably connected to selected ones of said functional elements configured into said reprogrammable logic devices, said reprogrammable logic devices also having an input demultiplexer and an output multiplexer implemented at at least one input/output terminal, said input demultiplexer having a select input electrically connected to a clock signal, said output multiplexer having a select input electrically connected to said clock signal, said input demultiplexer receiving a time-multiplexed signal and dividing said time-multiplexed signal into one or more internal signals, said output multiplexer combining one or more internal signals onto a first single physical interconnection;

a plurality of reprogrammable interconnect devices disposed on said printed circuit boards, each of said reprogrammable interconnect devices having input/output terminals and internal circuitry which can be reprogrammably configured to provide interconnections between selected ones of said input/output terminals, said plurality of reprogrammable interconnect devices also having an input demultiplexer and an output multiplexer implemented at at least one input/output terminal, said input demultiplexer having a select input electrically connected to said clock signal, said output multiplexer having a select input electrically connected to said clock signal, said input demultiplexer receiving a time-multiplexed input signal and dividing it into one or more component signals, said output multiplexer combining said one or more component signals or other component signals onto a second single physical interconnection; and

a set of fixed electrical conductors connecting said programmable input/output terminals on said reprogrammable logic devices to said input/output terminals on said reprogrammable interconnect devices such that each of said reprogrammable interconnect devices is connected to at least one but not all of said programmable input/output terminals on each of said reprogrammable logic devices.

25. The electrically reconfigurable logic assembly of claim 24 wherein said clock signal is a synchronous signal.