Method of manufacturing an insulated gate semiconductor device

• US 5,960,264 A
• Filed: 09/29/1997
• Issued: 09/28/1999
• Est. Priority Date: 07/21/1995
• Status: Expired due to Term

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation), Mitsubishi Electric Corporation
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Takahashi, Hideki
• Primary Examiner(s): Nguyen, Tuan H.
• Application Number:
  US08/939,496
• Time in Patent Office: 729 Days
• Field of Search: 438/133, 438/135, 438/137, 438/138, 438/268, 438/269, 438/270, 438/271
• US Class Current: 438/133
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A parasitic transistor of an insulated gate semiconductor device does not easily turn on, so that an SOA of the insulated gate semiconductor device is improved. P⁺ semiconductor layers (45) having a higher impurity concentration than that N⁺ emitter layers (44) are disposed so that the P⁺ semiconductor layers (45) overlap adjacent edges of the N⁺ emitter layers (44) of a U-type IGBT and so that bottom portions of the P⁺ semiconductor layers (45) contact P base layers (43). An emitter electrode (51) contacts the P base layers (43) through the P⁺ semiconductor layers (45). A trench pitch is small, and therefore, a parasitic transistor which is formed by an N⁺ emitter region (4), a P base layer (3) and an N^- layer (2) does not easily turn on.

Claims

1. A method of manufacturing an insulated gate semiconductor device, comprising:

a first step of preparing a semiconductor substrate which comprises a first semiconductor layer of a first conductivity type being exposed on a first major surface of said semiconductor substrate;

a second step of implanting impurities of a second conductivity type into said first major surface of said semiconductor substrate to thereby form a second semiconductor layer of the second conductivity type;

a third step of selectively implanting impurities of the first conductivity type, and diffusing said impurities of the first conductivity type in a surface of said second semiconductor layer to thereby selectively form a third semiconductor layer of the first conductivity type having a higher impurity concentration than said first semiconductor layer;

a fourth step of forming a shielding film on said first major surface, forming an opening in said shielding film on a portion of a surface of said third semiconductor layer so that said opening extends along a surface of said shielding film, selectively removing a semiconductor down to said first semiconductor layer while using as a mask said shielding film which includes said opening to thereby form a groove-shaped inner wall which defines a groove, and thereafter removing said shielding film;

a fifth step of forming an insulation film on a surface of said groove-shaped inner wall and on said first major surface;

a sixth step of stacking a conductive material on said insulation film so that said groove is filled up;

a seventh step of removing said conductive material, while leaving said insulation film, until a surface of a portion of said insulation film formed on said first major surface is exposed;

an eighth step of selectively implanting impurities of the second conductivity type at a higher impurity concentration than that of said third semiconductor layer into a portion of said first major surface on which said second semiconductor layer is selectively exposed, and diffusing said impurities of the second conductivity type to thereby selectively form a fourth semiconductor layer of the second conductivity type connecting said second semiconductor layer;

a ninth step of stacking an insulation material on said portion of said insulation film, which is exposed at said seventh step, and on a surface of said conductive material;

a tenth step of stacking a resist on a surface of said insulation material, forming an opening therein which surrounds said fourth semiconductor layer, and a portion of said third semiconductor layer which is adjacent to said fourth semiconductor layer, selectively removing said insulation material and said insulation film while using said resist as a mask which includes said opening to thereby expose said fourth and said third semiconductor layers;

an eleventh step of stacking a conductive layer on said third and fourth semiconductor layers, which are exposed after said tenth step and on said surface of said insulation material; and

a twelfth step of stacking a conductive layer on a second major surface of said semiconductor substrate which is on an opposite side to said first major surface.

2. A method of manufacturing an insulated gate semiconductor device, comprising:

a first step of preparing a semiconductor substrate which comprises a first semiconductor layer of a first conductivity type being exposed on a first major surface of said semiconductor substrate;

a second step of implanting impurities of a second conductivity type into said first major surface of said semiconductor substrate to thereby form a second semiconductor layer of the second conductivity type;

a third step of selectively implanting impurities of the first conductivity type, and diffusing said impurities of the first conductivity type in a surface of said second semiconductor layer to thereby selectively form third semiconductor layers of the first conductivity type in a shape of columns arranged parallel to each other having a higher impurity concentration than said first semiconductor layer;

a fourth step of forming a shielding film on said first major surface, forming an opening in said shielding film on a portion of a surface of said third semiconductor layers so that said opening extends along a surface of columns of said third semiconductor layers, selectively removing a semiconductor down to said first semiconductor layer while using said shielding film as a mask which includes said opening to thereby form groove-shaped inner walls which define grooves, and thereafter removing said shielding film;

a fifth step of forming an insulation film on surfaces of said groove-shaped inner walls and on said first major surface;

a sixth step of stacking a conductive material on said insulation film so that said grooves are filled up;

a seventh step of removing said conductive material, while leaving said insulation film until a surface of a portion of said insulation film which is formed on said first major surface is exposed;

an eighth step of selectively implanting impurities of the second conductivity type at a higher impurity concentration than that of said third semiconductor layers into a portion of said first major surface on which said second semiconductor layer is selectively exposed, and diffusing said impurities of the second conductivity type to thereby selectively form a fourth semiconductor layer of the second conductivity type connecting said second semiconductor layer;

a ninth step of stacking an insulation material on said portion of said insulation film, which is exposed after said seventh step, and on a surface of said conductive material;

a tenth step of stacking a resist on a surface of said insulation material, forming an opening therein which surrounds said fourth semiconductor layer and portions of said third semiconductor layers which are adjacent to said fourth semiconductor layer, selectively removing said insulation material and said insulation film while using said resist as a mask which includes said opening to thereby expose said fourth and said third semiconductor layers;

an eleventh step of stacking a conductive layer on said third and fourth semiconductor layers which are exposed after said tenth step and on said surface of said insulation material; and

a twelfth step of stacking a conductive layer on a second major surface of said semiconductor substrate which is on an opposite side to said first major surface.

3. A method of manufacturing an insulated gate semiconductor device, comprising:

a first step of preparing a semiconductor substrate which comprises a first semiconductor layer of a first conductivity type being exposed on a first major surface of said semiconductor substrate;

a second step of implanting impurities of a second conductivity type into said first major surface of said semiconductor substrate to thereby form a second semiconductor layer of the second conductivity type;

a third step of selectively implanting impurities of the first conductivity type, and diffusing said impurities of the first conductivity type in a surface of said second semiconductor layer to thereby selectively form third semiconductor layers of the first conductivity type having a higher impurity concentration than said first semiconductor layer;

a fourth step of forming a shielding film on said first major surface, forming an opening in said shielding film on a portion of a surface of said third semiconductor layers so that said opening extends along a surface of columns of said third semiconductor layers, selectively removing a semiconductor down to said first semiconductor layer while using said shielding film as a mask which includes said opening to thereby form groove-shaped inner walls which define grooves, and thereafter removing said shielding film;

a fifth step of forming an insulation film on surfaces of said groove-shaped inner walls and on said first major surface;

a sixth step of stacking a conductive material on said insulation film so that said grooves are filled up;

a seventh step of removing said conductive material, while leaving said insulation film until a surface of a portion of said insulation film which is formed on said first major surface is exposed;

an eighth step of selectively implanting impurities of the second conductivity type at a higher impurity concentration than that of said third semiconductor layers into a portion of said first major surface on which said second semiconductor layer is selectively exposed, and diffusing said impurities of the second conductivity type to thereby selectively form a fourth semiconductor layer of the second conductivity type connecting said second semiconductor layer;

a ninth step of stacking an insulation material on said portion of said insulation film, which is exposed after said seventh step, and on a surface of said conductive material;

a tenth step of stacking a resist on a surface of said insulation material, forming an opening therein which surrounds said fourth semiconductor layer and portions of said third semiconductor layers which are adjacent to said fourth semiconductor layer, selectively removing said insulation material and said insulation film while using said resist as a mask which includes said opening to thereby expose said fourth and said third semiconductor layers;

an eleventh step of stacking a conductive layer on said third and fourth semiconductor layers which are exposed after said tenth step and on said surface of said insulation material; and

a twelfth step of stacking a conductive layer on a second major surface of said semiconductor substrate which is on an opposite side to said first major surface, wherein at said third step, said third semiconductor layers are formed in a shape including columns and a link portion linking adjacent two of said columns and at said tenth step, said opening of said resist is formed to surround said fourth and said third semiconductor layers except for portions of said surfaces of said third semiconductor layers which are adjacent to and along said inner walls.

4. A method of manufacturing an insulated gate semiconductor device, comprising:

a first step of preparing a semiconductor substrate which comprises a first semiconductor layer of a first conductivity type being exposed on a first major surface of said semiconductor substrate;

a second step of implanting impurities of a second conductivity type into a! said first major surface of said semiconductor substrate to thereby form a second semiconductor layer of the second conductivity type;

a third step of selectively implanting impurities of the first conductivity type, and diffusing said impurities of the first conductivity type in a surface of said second semiconductor layer to thereby form third semiconductor layers of the first conductivity type in a shape of columns arranged parallel to each other and a link portion linking adjacent two of said columns having a higher impurity concentration than said first semiconductor layer;

a fourth step of forming a shielding film on said first major surface, forming an opening in said shielding film on a portion of a surface of said third semiconductor layers so that said opening extends along a surface of columns of said third semiconductor layers, selectively removing a semiconductor down to said first semiconductor layer while using said shielding film as a mask which includes said opening to thereby form groove-shaped inner walls which define grooves, and thereafter removing said shielding film;

a fifth step of forming an insulation film on surfaces of said groove-shaped inner walls and on said first major surface;

a sixth step of stacking a conductive material on said insulation film so that said grooves are filled up;

a seventh step of removing said conductive material while leaving said insulation film until a surface of a portion of said insulation film which is formed on said first major surface is exposed;

an eighth step of selectively implanting impurities of the second conductivity type at a higher impurity concentration than that of said third semiconductor layers into a portion of said first major surface on which said second semiconductor layer is selectively exposed, and diffusing said impurities of the second conductivity type to thereby selectively form a fourth semiconductor layer of the second conductivity type connecting said second semiconductor layer;

a ninth step of stacking an insulation material on said portion of said insulation film, which is exposed after said seventh step, and on a surface of said conductive material;

a tenth step of stacking a resist on a surface of said insulation material, forming an opening therein which surrounds said fourth semiconductor layer and said third semiconductor layers, except for said portions of said surfaces of said third semiconductor layers which are adjacent to and along said inner walls and except for a portion of a surface of said fourth semiconductor layer, selectively removing said insulation material and said insulation film while using said resist as a mask which includes said opening to thereby expose said fourth semiconductor layer and said third semiconductor layers;

an eleventh step of stacking a conductive layer on said third and fourth semiconductor layers which are exposed after said tenth step and on said surface of said insulation material; and

a twelfth step of stacking a conductive layer on a second major surface of said semiconductor substrate which is on an opposite side to said first major surface.

5. A method of manufacturing an insulated gate semiconductor device, comprising:

a first step of preparing a semiconductor substrate which comprises a first semiconductor layer of a first conductivity type being exposed on a first major surface of said semiconductor substrate;

a second step of implanting impurities of a second conductivity type into said first major surface of said semiconductor substrate to thereby form a second semiconductor layer of the second conductivity type;

a third step of selectively implanting impurities of the first conductivity type, and diffusing said impurities of the first conductivity type in a surface of said second semiconductor layer to thereby selectively form third semiconductor layers of the first conductivity type in a shape of columns arranged parallel to each other and a link portion linking adjacent two of said columns having a higher impurity concentration than said first semiconductor layer;

a fourth step of forming a shielding film on said first major surface, forming an opening in said shielding film on a portion of a surface of said third semiconductor layers so that said opening extends along a surface of columns of said third semiconductor layers, selectively removing a semiconductor down to said first semiconductor layer while using said shielding film as a mask which includes said opening to thereby form groove-shaped inner walls which define grooves, and thereafter removing said shielding film;

a fifth step of forming an insulation film on surfaces of said groove-shaped inner walls and on said first major surface;

a sixth step of stacking a conductive material on said insulation film so that said grooves are filled up;

a seventh step of removing said conductive material while leaving said insulation film until a surface of a portion of said insulation film which is formed on said first major surface is exposed;

an eighth step of stacking an insulation material on a portion of said insulation film which is exposed after said seventh step, and said surface of said conductive material;

a ninth step of stacking a resist on a surface of said insulation material, forming an opening therein which surrounds said second semiconductor and third semiconductor layers, except for portions of surfaces of said third semiconductor layers which are adjacent to and along said inner walls and except for a portion of said exposed surface of said second semiconductor layer which is adjacent to said portions of said surfaces of said third semiconductor layers, selectively removing said insulation material and said insulation film while using a resist pattern which includes said opening to thereby expose said second semiconductor layer and said portions of said third semiconductor layers which are adjacent to said second semiconductor layer;

a tenth step of stacking a conductive layer on said second and third semiconductor layer which is exposed after said ninth step and on said surface of said insulation material; and

an eleventh step of stacking a conductive layer on a second major surface of said semiconductor substrate which is on an opposite side to said first major surface.

6. A method of manufacturing an insulated gate semiconductor device, comprising:

a first step of forming a semiconductor substrate which comprises a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type disposed on a surface of said first semiconductor layer;

a second step of implanting impurities of the first conductivity type into a first major surface of said semiconductor substrate which is on the second semiconductor layer side of said semiconductor substrate to thereby form a third semiconductor layer of the first conductivity type;

a third step of stacking a resist on said first major surface, selectively removing said resist to obtain a resist pattern, selectively implanting impurities of the second conductivity type using said resist pattern as a mask, and diffusing said impurities of the second conductivity type in a surface of said third semiconductor layer to thereby selectively form a fourth semiconductor layer of the second conductivity type having a higher impurity concentration than said second semiconductor layer;

a fourth step of forming a shielding film on said first major surface, forming an opening in said shielding film on a portion of a surface of said fourth semiconductor layer so that said opening extends along a surface of said shielding film, selectively removing a semiconductor down to said second semiconductor layer while using as a mask said shielding film which includes said opening to thereby form a groove-shaped inner wall which defines a groove, and thereafter removing said shielding film;

a fifth step of forming an insulation film on a surface of said groove-shaped inner wall and on said first major surface;

a sixth step of stacking a conductive material on said insulation film so that said groove is filled up;

a seventh step of removing said conductive material, while leaving said insulation film, until a surface of a portion of said insulation film formed on said first major surface is exposed;

an eighth step of stacking a resist on a portion of said insulation film, which is exposed on said first major surface after said seventh step, and said surface of said conductive material, forming an opening therein at such a position as to surround an area which corresponds to said resist which is selectively left at said third step and to surround a portion of said surface of said fourth semiconductor layer which is adjacent to said area, selectively implanting impurities of the first conductivity type at a higher impurity concentration than that of said fourth semiconductor layer through said insulation film while using said resist as a mask which includes said opening, and diffusing said impurities of the first conductivity type to thereby selectively form a fifth semiconductor layer of the first conductivity type connecting said third semiconductor layer;

a ninth step of stacking an insulation material on said portion of said insulation film, which is exposed at said seventh step, and on a surface of said conductive material;

a tenth step of stacking a resist on a surface of said insulation material, forming an opening therein which surrounds said fifth semiconductor layer, and a portion of said fourth semiconductor layer which is adjacent to said fifth semiconductor layer, selectively removing said insulation material and said insulation film while using said resist as a mask which includes said opening to thereby expose said fifth and said fourth semiconductor layers;

an eleventh step of stacking a conductive layer on said fourth and fifth semiconductor layers, which are exposed after said tenth step and on said surface of said insulation material; and

a twelfth step of stacking a conductive layer on a second major surface of said semiconductor substrate which is on an opposite side to said first major surface.

7. A method of manufacturing an insulated gate semiconductor device, comprising:

a first step of forming a semiconductor substrate which comprises a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type disposed on a surface of said first semiconductor layer;

a second step of implanting impurities of the first conductivity type into a first major surface of said semiconductor substrate which is on the second semiconductor layer side of said semiconductor substrate to thereby form a third semiconductor layer of the first conductivity type;

a third step of stacking a resist on said first major surface, selectively removing said resist to leave a portion of said resist as a plurality of regions which are arranged parallel to each other in the shape of columns so that a resist pattern is formed, selectively implanting impurities of the second conductivity type while using said resist pattern as a mask, and diffusing said impurities of the second conductivity type in a surface of said third semiconductor layer to thereby selectively form fourth semiconductor layers of the second conductivity type having a higher impurity concentration than said second semiconductor layer;

a fourth step of forming a shielding film on said first major surface, forming an opening in said shielding film on a portion of a surface of said fourth semiconductor layers so that said opening extends along a surface of columns of said fourth semiconductor layers, selectively removing a semiconductor down to said second semiconductor layer while using said shielding film as a mask which includes said opening to thereby form groove-shaped inner walls which define grooves, and thereafter removing said shielding film;

a fifth step of forming an insulation film on surfaces of said groove-shaped inner walls and on said first major surface;

a sixth step of stacking a conductive material on said insulation film so that said grooves are filled up;

a seventh step of removing said conductive material, while leaving said insulation film, until a surface of a portion of said insulation film which is formed on said first major surface is exposed;

an eighth step of stacking a resist on a portion of said insulation film, which is exposed on said first major surface after said seventh step, and said surface of said conductive material, forming an opening therein at such a position as to surround an area which corresponds to said resist which is left in the shape of columns at said third step and to surround portions of surfaces of said fourth semiconductor layers which are adjacent to said area, selectively implanting impurities of the first conductivity type at a higher impurity concentration than that of said fourth semiconductor layers through said insulation film while using said resist as a mask which includes said opening, and diffusing said impurities of the first conductivity type to thereby selectively form a fifth semiconductor layer of the first conductivity type connecting said third semiconductor layer;

a ninth step of stacking an insulation material on said portion of said insulation film, which is exposed after said seventh step, and on a surface of said conductive material;

a tenth step of stacking a resist on a surface of said insulation material, forming an opening therein which surrounds said fifth semiconductor layer and portions of said fourth semiconductor layers which are adjacent to said fifth semiconductor layer, selectively removing said insulation material and said insulation film while using said resist as a mask which includes said opening to thereby expose said fifth and said fourth semiconductor layers;

an eleventh step of stacking a conductive layer on said fourth and fifth semiconductor layers which are exposed after said tenth step and on said surface of said insulation material; and

a twelfth step of stacking a conductive layer on a second major surface of said semiconductor substrate which is on an opposite side to said first major surface.

8. The method of claim 7, wherein at said third step, said portion of said resist is left as a plurality of regions which are scattered in the shape of columns and are arranged parallel to each other to thereby obtain said resist pattern, and at said tenth step, said opening of said resist is formed to surround said fifth and said fourth semiconductor layers except for portions of said surfaces of said fourth semiconductor layers which are adjacent to and along said inner walls.

9. A method of manufacturing an insulated gate semiconductor device, comprising:

a first step of forming a semiconductor substrate which comprises a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type disposed on a surface of said first semiconductor layer;

a second step of implanting impurities of the first conductivity type into a first major surface of said semiconductor substrate which is on the second semiconductor layer side of said semiconductor substrate to thereby form a third semiconductor layer of the first conductivity type;

a third step of stacking a resist on said first major surface, selectively removing said resist to leave a portion of said resist as a plurality of regions which are scattered in the shape of columns and arranged parallel to each other so that a resist pattern is formed, selectively implanting impurities of the second conductivity type using said resist pattern as a mask, and diffusing said impurities of the second conductivity type in a surface of said third semiconductor layer to thereby form fourth semiconductor layers of the second conductivity type having a higher impurity concentration than said second semiconductor layer;

a fourth step of forming a shielding film on said first major surface, forming an opening in said shielding film on a portion of a surface of said fourth semiconductor layers so that said opening extends along a surface of columns of said fourth semiconductor layers, selectively removing a semiconductor down to said second semiconductor layer while using said shielding film as a mask which includes said opening to thereby form groove-shaped inner walls which define grooves, and thereafter removing said shielding film;

a fifth step of forming an insulation film on surfaces of said groove-shaped inner walls and on said first major surface;

a sixth step of stacking a conductive material on said insulation film so that said grooves are filled up;

a seventh step of removing said conductive material, while leaving said insulation film, until a surface of a portion of said insulation film which is formed on said first major surface is exposed;

an eighth step of stacking a resist on a portion of said insulation film, which is exposed on said first major surface after said seventh step, and said surface of said conductive material, forming an opening therein at such a position as to surround an area which corresponds to said resist which is left in the shape of columns at said third step and to surround portions of surfaces of said fourth semiconductor layers which are adjacent to said area, selectively implanting impurities of the first conductivity type at a higher impurity concentration than that of said fourth semiconductor layers through said insulation film while using said resist as a mask which includes said opening, and diffusing said impurities of the first conductivity type to thereby selectively form a fifth semiconductor layer of the first conductivity type connecting said third semiconductor layer;

a ninth step of stacking an insulation material on said portion of said insulation film, which is exposed after said seventh step, and on a surface of said conductive material;

a tenth step of stacking a resist on a surface of said insulation material, forming an opening therein which surrounds said fifth semiconductor layer and said fourth semiconductor layers, except for said portions of said surfaces of said fourth semiconductor layers which are adjacent to and along said inner walls and except for a portion of a surface of said fifth semiconductor layer, selectively removing said insulation material and said insulation film while using said resist as a mask which includes said opening to thereby expose said fifth semiconductor layer and said fourth semiconductor layers;

an eleventh step of stacking a conductive layer on said fourth and fifth semiconductor layers which are exposed after said tenth step and on said surface of said insulation material; and

a twelfth step of stacking a conductive layer on a second major surface of said semiconductor substrate which is on an opposite side to said first major surface.

10. A method of manufacturing an insulated gate semiconductor device, comprising:

a first step of forming a semiconductor substrate which comprises a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type disposed on a surface of said first semiconductor layer;

a second step of implanting impurities of the first conductivity type into a first major surface of said semiconductor substrate which is on the second semiconductor layer side of said semiconductor substrate to thereby form a third semiconductor layer of the first conductivity type;

a third step of stacking a resist on said first major surface, selectively removing said resist to leave a portion of said resist as a plurality of regions which are scattered in the shape of columns and arranged parallel to each other so that a resist pattern is formed, selectively implanting impurities of the second conductivity type using said resist pattern as a mask, and diffusing said impurities of the second conductivity type in a surface of said third semiconductor layer so as to leave a portion of an exposed surface of said third semiconductor layer which is covered with said resist to thereby selectively form fourth semiconductor layers of the second conductivity type having a higher impurity concentration than said second semiconductor layer;

a fourth step of forming a shielding film on said first major surface forming an opening in said shielding film on a portion of a surface of said fourth semiconductor layers so that said opening extends along a surface of columns of said fourth semiconductor layers, selectively removing a semiconductor down to said second semiconductor layer while using said shielding film as a mask which includes said opening to thereby form groove-shaped inner walls which define grooves, and thereafter removing said shielding film;

a fifth step of forming an insulation film on surfaces of said groove-shaped inner walls and on said first major surface;

a sixth step of stacking a conductive material on said insulation film so that said grooves are filled up;

a seventh step of removing said conductive material, while leaving said insulation film, until a surface of a portion of said insulation film which is formed on said first major surface is exposed;

an eighth step of stacking an insulation material on a portion of said insulation film which is exposed after said seventh step, and said surface of said conductive material;

a ninth step of stacking a resist on a surface of said insulation material, forming an opening therein which surrounds said third semiconductor and fourth semiconductor layers, except for portions of surfaces of said fourth semiconductor layers which are adjacent to and along said inner walls and except for a portion of said exposed surface of said third semiconductor layer which is adjacent to said portions of said surfaces of said fourth semiconductor layers, selectively removing said insulation material and said insulation film while using a resist pattern which includes said opening to thereby expose said third semiconductor layer and said portions of said fourth semiconductor layers which are adjacent to said third semiconductor layer;

a tenth step of stacking a conductive layer on said third and fourth semiconductor layer which is exposed after said ninth step and on said surface of said insulation material; and

an eleventh step of stacking a conductive layer on said second major surface of said semiconductor substrate which is on an opposite side to said first major surface.

11. A method of manufacturing an insulated gate semiconductor device, comprising:

a first step of forming a semiconductor substrate which comprises a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type disposed on a surface of said first semiconductor layer;

a second step of implanting impurities of the first conductivity type into a first major surface of said semiconductor substrate which is on the second semiconductor layer side of said semiconductor substrate to thereby form a third semiconductor layer of the first conductivity type;

a third step of selectively implanting impurities of the second conductivity type, and diffusing said impurities of the second conductivity type in a surface of said third semiconductor layer to thereby selectively form a fourth semiconductor layer of the second conductivity type having a higher impurity concentration than said second semiconductor layer;

a fourth step of forming a shielding film on said first major surface, forming an opening in said shielding film on a portion of a surface of said fourth semiconductor layer so that said opening extends along a surface of said shielding film, selectively removing a semiconductor down to said second semiconductor layer while using as a mask said shielding film which includes said opening to thereby form a groove-shaped inner wall which defines a groove, and thereafter removing said shielding film;

a fifth step of forming an insulation film on a surface of said groove-shaped inner wall and on said first major surface;

a sixth step of stacking a conductive material on said insulation film so that said groove is filled up;

a seventh step of removing said conductive material, while leaving said insulation film, until a surface of a portion of said insulation film formed on said first major surface is exposed;

an eighth step of selectively implanting impurities of the first conductivity type at a higher impurity concentration than that of said fourth semiconductor layer into a portion of said first major surface on which said third semiconductor layer is selectively exposed, and diffusing said impurities of the first conductivity type to thereby selectively form a fifth semiconductor layer of the first conductivity type connecting said third semiconductor layer;

a ninth step of stacking an insulation material on said portion of said insulation film, which is exposed at said seventh step, and on a surface of said conductive material;

a tenth step of stacking a resist on a surface of said insulation material, forming an opening therein which surrounds said fifth semiconductor layer, and a portion of said fourth semiconductor layer which is adjacent to said fifth semiconductor layer, selectively removing said insulation material and said insulation film while using said resist as a mask which includes said opening to thereby expose said fifth and said fourth semiconductor layers;

an eleventh step of stacking a conductive layer on said fourth and fifth semiconductor layers, which are exposed after said tenth step and on said surface of said insulation material; and

a twelfth step of stacking a conductive layer on a second major surface of said semiconductor substrate which is on an opposite side to said first major surface.

12. A method of manufacturing an insulated gate semiconductor device, comprising:

a first step of forming a semiconductor substrate which comprises a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type disposed on a surface of said first semiconductor layer;

a second step of implanting impurities of the first conductivity type into a first major surface of said semiconductor substrate which is on the second semiconductor layer side of said semiconductor substrate to thereby form a third semiconductor layer of the first conductivity type;

a third step of selectively implanting impurities of the second conductivity type, and diffusing said impurities of the second conductivity in a surface of said third semiconductor layer to thereby selectively form fourth semiconductor layers of the second conductivity type in a shape of columns parallel to each other having a higher impurity concentration than said second semiconductor layer;

a fourth step of forming a shielding film on said first major surface, forming an opening in said shielding film on a portion of a surface of said fourth semiconductor layers so that said opening extends along a surface of columns of said fourth semiconductor layers, selectively removing a semiconductor down to said second semiconductor layer while using said shielding film as a mask which includes said opening to thereby form groove-shaped inner walls which define grooves, and thereafter removing said shielding film;

a fifth step of forming an insulation film on surfaces of said groove-shaped inner walls and on said first major surface;

a sixth step of stacking a conductive material on said insulation film so that said grooves are filled up;

a seventh step of removing said conductive material, while leaving said insulation film, until a surface of a portion of said insulation film which is formed on said first major surface is exposed;

an eighth step of selectively implanting impurities of the first conductivity type at a higher impurity concentration than that of said fourth semiconductor layers into a portion of said first major surface on which said third semiconductor layer is selectively exposed, and diffusing said impurities of the first conductivity type to thereby selectively form a fifth semiconductor layer of the first conductivity type connecting said third semiconductor layer;

a ninth step of stacking an insulation material on said portion of said insulation film, which is exposed after said seventh step, and on a surface of said conductive material;

a tenth step of stacking a resist on a surface of said insulation material, forming an opening therein which surrounds said fifth semiconductor layer and portions of said fourth semiconductor layers which are adjacent to said fifth semiconductor layer, selectively removing said insulation material and said insulation film while using said resist as a mask which includes said opening to thereby expose said fifth and said fourth semiconductor layers;

an eleventh step of stacking a conductive layer on said fourth and fifth semiconductor layers which are exposed after said tenth step and on said surface of said insulation material; and

a twelfth step of stacking a conductive layer on a second major surface of said semiconductor substrate which is on an opposite side to said first major surface.

13. A method of manufacturing an insulated gate semiconductor device, comprising:

a first step of forming a semiconductor substrate which comprises a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type disposed on a surface of said first semiconductor layer;

a second step of implanting impurities of the first conductivity type into a first major surface of said semiconductor substrate which is on the second semiconductor layer side of said semiconductor substrate to thereby form a third semiconductor layer of the first conductivity type;

a third step of selectively implanting impurities of the second conductivity type, and diffusing said impurities of the second conductivity type in a surface of said third semiconductor layer to thereby form fourth semiconductor layers of the second conductivity type having a higher impurity concentration than said second semiconductor layer;

a fourth step of forming a shielding film on said first major surface, forming an opening in said shielding film on a portion of a surface of said fourth semiconductor layers so that said opening extends along a surface of columns of said fourth semiconductor layers, selectively removing a semiconductor down to said second semiconductor layer while using said shielding film as a mask which includes said opening to thereby form groove-shaped inner walls which define grooves, and thereafter removing said shielding film;

a fifth step of forming an insulation film on surfaces of said groove-shaped inner walls and on said first major surface;

a sixth step of stacking a conductive material on said insulation film so that said grooves are filled up;

a seventh step of removing said conductive material, while leaving said insulation film, until a surface of a portion of said insulation film which is formed on said first major surface is exposed;

an eighth step of selectively implanting impurities of the first conductivity type at a higher impurity concentration than that of said fourth semiconductor layers into a portion of said first major surface on which said third semiconductor layer is selectively exposed, and diffusing said impurities of the first conductivity type to thereby selectively form a fifth semiconductor layer of the first conductivity type connecting said third semiconductor layer;

a ninth step of stacking an insulation material on said portion of said insulation film, which is exposed after said seventh step, and on a surface of said conductive material;

a tenth step of stacking a resist on a surface of said insulation material, forming an opening therein which surrounds said fifth semiconductor layer and said fourth semiconductor layers, except for said portions of said surfaces of said fourth semiconductor layers which are adjacent to and along said inner walls and except for a portion of a surface of said fifth semiconductor layer, selectively removing said insulation material and said insulation film while using said resist as a mask which includes said opening to thereby expose said fifth semiconductor layer and said fourth semiconductor layers;

an eleventh step of stacking a conductive layer on said fourth and fifth semiconductor layers which are exposed after said tenth step and on said surface of said insulation material; and

a twelfth step of stacking a conductive layer on a second major surface of said semiconductor substrate which is on an opposite side to said first major surface, said fourth semiconductor layers being formed in a shape including columns and a link portion linking adjacent two of said columns,

wherein at said third step and at said tenth step, said opening of said resist is formed to surround said fifth and said fourth semiconductor layers except for portions of said surfaces of said fourth semiconductor layers which are adjacent to and along said inner walls.

14. A method of manufacturing an insulated gate semiconductor device, comprising:

a first step of forming a semiconductor substrate which comprises a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type disposed on a surface of said first semiconductor layer;

a second step of implanting impurities of the first conductivity type into a first major surface of said semiconductor substrate which is on the second semiconductor layer side of said semiconductor substrate to thereby form a third semiconductor layer of the first conductivity type;

a third step of selectively implanting impurities of the second conductivity type, and diffusing said impurities of the second conductivity type in a surface of said third semiconductor layer to thereby form fourth semiconductor layers of the second conductivity type in a shape of columns arranged parallel to each other and a link portion linking adjacent two of said columns having a higher impurity concentration than said second semiconductor layer;

a fourth step of forming a shielding film on said first major surface, forming an opening in said shielding film on a portion of a surface of said fourth semiconductor layers so that said opening extends along a surface of columns of said fourth semiconductor layers, selectively removing a semiconductor down to said second semiconductor layer while using said shielding film as a mask which includes said opening to thereby form groove-shaped inner walls which define grooves, and thereafter removing said shielding film;

a fifth step of forming an insulation film on surfaces of said groove-shaped inner walls and on said first major surface;

a sixth step of stacking a conductive material on said insulation film so that said grooves are filled up;

a seventh step of removing said conductive material while leaving said insulation film until a surface of a portion of said insulation film which is formed on said first major surface is exposed;

an eighth step of selectively implanting impurities of the first conductivity type at a higher impurity concentration than that of said fourth semiconductor layers into a portion of said first major surface on which said third semiconductor layer is selectively exposed, and diffusing said impurities of the first conductivity type to thereby selectively form a fifth semiconductor layer of the first conductivity type connecting said third semiconductor layer;

a ninth step of stacking an insulation material on said portion of said insulation film, which is exposed after said seventh step, and on a surface of said conductive material;

a tenth step of stacking a resist on a surface of said insulation material, forming an opening therein which surrounds said fifth semiconductor layer and said fourth semiconductor layers, except for said portions of said surfaces of said fourth semiconductor layers which are adjacent to and along said inner walls and except for a portion of a surface of said fifth semiconductor layer, selectively removing said insulation material and said insulation film while using said resist as a mask which includes said opening to thereby expose said fifth semiconductor layer and said fourth semiconductor layers;

an eleventh step of stacking a conductive layer on said fourth and fifth semiconductor layers which are exposed after said tenth step and on said surface of said insulation material; and

a twelfth step of stacking a conductive layer on a second major surface of said semiconductor substrate which is on an opposite side to said first major surface.

15. A method of manufacturing an insulated gate semiconductor device, comprising:

a first step of forming a semiconductor substrate which comprises a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type disposed on a surface of said first semiconductor layer;

a second step of implanting impurities of the first conductivity type into a first major surface of said semiconductor substrate which is on the second semiconductor layer side of said semiconductor substrate to thereby form a third semiconductor layer of the first conductivity type;

a third step of selectively implanting impurities of the second conductivity type, and diffusing said impurities of the second conductivity type in a surface of said third semiconductor layer to thereby selectively form fourth semiconductor layers of the second conductivity type in a shape of columns arranged parallel to each other and a link portion linking adjacent two of said columns having a higher impurity concentration than said second semiconductor layer;

a fourth step of forming a shielding film on said first major surface, forming an opening in said shielding film on a portion of a surface of said fourth semiconductor layers so that said opening extends along a surface of columns of said fourth semiconductor layers, selectively removing a semiconductor down to said second semiconductor layer while using said shielding film as a mask which includes said opening to thereby form groove-shaped inner walls which define grooves, and thereafter removing said shielding film;

a fifth step of forming an insulation film on surfaces of said groove-shaped inner walls and on said first major surface;

a sixth step of stacking a conductive material on said insulation film so that said grooves are filled up;

a seventh step of removing said conductive material while leaving said insulation film until a surface of a portion of said insulation film which is formed on said first major surface is exposed;

an eighth step of stacking an insulation material on a portion of said insulation film which is exposed after said seventh step, and said surface of said conductive material;

a ninth step of stacking a resist on a surface of said insulation material, forming an opening therein which surrounds said third semiconductor and fourth semiconductor layers, except for portions of surfaces of said fourth semiconductor layers which are adjacent to and along said inner walls and except for a portion of said exposed surface of said third semiconductor layer which is adjacent to said portions of said surfaces of said fourth semiconductor layers, selectively removing said insulation material and said insulation film while using a resist pattern which includes said opening to thereby expose said third semiconductor layer and said portions of said fourth semiconductor layers which are adjacent to said third semiconductor layer;

a tenth step of stacking a conductive layer on said third and fourth semiconductor layer which is exposed after said ninth step and on said surface of said insulation material; and

an eleventh step of stacking a conductive layer on said second major surface of said semiconductor substrate which is on an opposite side to said first major surface.