Short channel self-aligned VMOS field effect transistor

• US 5,960,271 A
• Filed: 03/17/1998
• Issued: 09/28/1999
• Est. Priority Date: 09/18/1996
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Fatemi, Homi, Wollesen, Donald L.
• Primary Examiner(s): TRINH, MICHAEL MANH
• Application Number:
  US09/042,786
• Time in Patent Office: 560 Days
• Field of Search: 438/197, 438/589, 438/270, 438/271, 438/272, 438/268, 438/301, 438/FOR 363, 148/DIG. 126
• US Class Current: 438/197
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/49 Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET H01L29/435 takes precedence
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence

Abstract

A field effect transistor with a trench or groove gate having V-shaped walls is formed in a semiconductor substrate and a gate oxide is grown on the V-shaped walls to the surface of substrate and filled with a gate electrode material, such a polysilicon. Preferably, the bottom of the V-shaped walls are rounded before the trench is filled. Source/drain impurities either are diffused or implanted into the areas of the substrate on both sides of the surface oxide of the V-shaped gate. Contacts are made to the source, drain, and gate within field isolation to complete the structure. The resultant FET structure comprises a self aligned V-shaped gate having conventional source and drain surrounded by field isolation but with an effective channel length (L_eff) of less than about one-half of the surface width of the gate. Preferably, the converging walls of the V-shaped gate end in a rounded concave bottom. Because of the V-shaped structure of the gate, the effective saturated length of the channel with drain voltage applied only extends from the edge of the source to just prior to the tip of the V-shaped structure in the interior of the semiconductor substrate. The drain side of the V-shaped structure becomes a depletion region due to the applied drain voltage. Due to this characteristic of such a structure, the surface width of the gate can be, for example, two or more times the distance of the desired channel length thereby permitting conventional lithography to be used to define the gate lengths much shorter than the lithographic limit.

Claims

1. A process of fabricating a short channel length field effect transistor (FET) comprising the steps of:

forming an insulating layer on a semiconductor substrate having an upper surface and with at least two crystalline planes, one plane being (100) and parallel with the upper surface and the other plane being (111);

forming an opening in said insulating layer;

forming a V-shaped trench in said substrate having a bottom in the substrate interior at the opening in the insulating layer by etching the substrate with an etchant having a preference for the (100) crystalline plane over the (111) crystalline plane, said trench having angled side walls converging toward each other at said bottom and forming said V-shaped trench with a rounded concave surface at the bottom and a top at the substrate surface having a width extending from one side wall to the other side wall;

forming a thin insulating layer on the angled side walls and a thicker insulating layer at said rounded concave surface of said trench having a lower side in contact with the substrate and an upper side;

filling the trench, with a material capable of being conductive and function as a gate of the FET, from the bottom to the top of the trench and having a top surface and a gate width at the substrate surface substantially the same as the width of the top of the trench;

forming source and drain regions in the substrate on opposite sides of the trench and, each having a metallurgical junction with an inner edge abutting one of the side walls of the trench to create a channel under the gate,

insulating the source, drain and gate from each other with an insulating material; and

forming conductive contacts to each of the source, drain and gate, the contacts being separated by an insulating material.

2. The method of claim 1 wherein, prior to forming said trench, a shallow diffusion region, of an opposite impurity type from the impurity of the source and drain, is formed in the semiconductor substrate as a channel diffusion and extends from below the source and drain to above the bottom of the gate and varies in concentration along the channel.

3. The method of claim 1 wherein, prior to the forming the trench, a diffusion region of an opposite impurity from the impurity of the source and drain is formed in the semiconductor substrate and extend from below the source and drain to below the bottom of the gate and is substantially uniform in concentration along the channel.

4. The method of claim 1 wherein, after the formation of said trench but prior to the filling of the trench, a diffusion region of an opposite impurity from the impurity of the source and drain is formed in the semiconductor substrate and surrounds the trench in a substantially uniform concentration and extends to a point below the top of the gate.

5. The method of claim 1 wherein the rounded concave bottom of the V-shaped trench is formed by forming, removing and reforming the gate insulating layer on the side walls of the trench at least once.

6. The method of claim 1 wherein the rounded concave bottom of the V-shaped trench is formed by growing a sacrificial oxide on the trench side walls, removing the oxide and growing the gate oxide on trench side walls.

7. The method of claim 1 wherein, prior to forming the conductive contacts, a metal silicide is formed in the semiconductor substrate of the source and drain regions and on the gate region, the metal silicide underlying the to-be formed conductive contacts.

8. The method of claim 1 wherein said gate material is polysilicon end is doped with an impurity during the formation of the source and drain.

9. The method of claim 1 includes the step of applying a voltage to said drain to form a channel between the metallurgical edge of said source adjacent the gate and the bottom of the trench, said channel being of a length of less than about one-half of the gate width at the surface of the substrate.

11. The method of claim 1 wherein, prior to forming said trench, a shallow diffusion region, of an opposite impurity type from the impurity of the source and drain, is formed in the semiconductor substrate as a channel diffusion and extends from below the source and drain to above the bottom of the gate and varies in concentration along the channel.

10. In a method of fabricating a short channel length V-shaped trench field effect transistor (VFET) in a semiconductor substrate and having a gate width at the surface of the substrate wherein, when a voltage is applied to form a channel, the channel is a length of less than one-half of said gate width, comprising the steps of:

forming an insulating layer on a semiconductor substrate having an upper surface and with at least two crystalline planes, one plane being (100) and parallel with the upper surface and the other plane being (111);

forming an opening in said insulating layer;

forming a V-shaped trench in said substrate having a bottom in the substrate interior at the opening in the insulating layer by etching the substrate with an etchant having a preference for the (100) crystalline plane over the (111) crystalline plane, said trench having angled side walls converging toward each other at said bottom and forming said V-shaped trench with a rounded concave surface at the bottom and a top at the substrate surface having a width extending from one side wall to the other side wall;

forming a thin insulating layer on the angled side walls and a thicker insulating layer at said rounded concave surface of said trench having a lower side in contact with the substrate and an upper side;

filling the trench, with a material capable of being conductive and function as a gate of the VFET, from the bottom to the top of the trench and having a top surface and a gate width at the substrate surface substantially the same as the width of the top of the trench;

forming source and drain regions in the substrate on opposite sides of the trench and, each having a metallurgical junction with an inner edge abutting one of the side walls of the trench to create the channel under the gate,

insulating the source, drain and gate from each other with an insulating material; and

forming conductive contacts to each of the source, drain and gate, the contacts being separated by an insulating material.

12. The method of claim 10 wherein, prior to the forming the trench, a diffusion region of an opposite impurity from the impurity of the source and drain is formed in the semiconductor substrate and extend from below the source and drain to below the bottom of the gate and is substantially uniform in concentration along the channel.

13. The method of claim 10 wherein, after the formation of the trench but prior to the filling of the trench, a diffusion region of an opposite impurity from the impurity of the source and drain is formed in the semiconductor substrate and surrounds the trench in a substantially uniform concentration and extends to a point below the top of the gate.

14. The method of claim 10 wherein the rounded concave bottom of the V-shaped trench is formed by forming, removing and reforming the gate insulating layer on the side walls of the trench at least once.

15. The method of claim 14 wherein the rounded concave bottom of the V-shaped trench is formed by growing a sacrificial oxide on the trench side walls, removing the oxide and growing the gate oxide on trench side walls.

16. The method of claim 10 wherein, prior to forming the conductive contacts, a metal silicide is formed in the semiconductor substrate of the source and drain regions and on the gate region, the metal silicide underlying the to-be formed conductive contacts.

17. The method of claim 10 wherein said gate material is polysilicon and is doped with an impurity during the formation of the source and drain.