Memory sharing architecture for a decoding in a computer system
DCFirst Claim
1. In a computer system having a main memory, a storage device having encoded data stored therein and a processor controlled by an operating system, an electronic device comprising:
- a decoding circuit coupled to receive and decode the encoded data from the storage device; and
a control circuit coupled to the decoding circuit, the processor and the main memory, the control circuit being configured to request continuous use of several portions of the main memory from the operating system, the portions of the main memory having noncontiguous addresses, and being configured to translate the noncontiguous addresses to contiguous addresses of a block of memory, andwherein the decoding circuit is configured to request at least some of the contiguous addresses of the block of memory, and wherein the control circuit translates the requested contiguous addresses of the block of memory to requested noncontiguous addresses and permits the decoding circuit to access the portions of the main memory.
5 Assignments
Litigations
6 Petitions
Accused Products
Abstract
A method and apparatus employing a memory management system that can be used with applications requiring a large contiguous block of memory, such as video decompression techniques (e.g., MPEG 2 decoding). The system operates with a computer and the computer'"'"'s operating system to request and employ approximately 500 4-kilobyte pages in two or more noncontiguous blocks of the main memory to construct a contiguous 2-megabyte block of memory. The system can employ, on a single chip, a direct memory access engine, a microcontroller, a small block of optional memory, and a video decoder circuit. The microcontroller retains the blocks of multiple pages of the main memory, and the page descriptors of these blocks, so as to lock down these blocks of memory and prohibit the operating system or other applications from using them. The microcontroller requests the page descriptors for each of the blocks, and programs a lookup table or memory mapping system in the on-chip memory to form a contiguous block of memory. As a result, the video decoder circuit can perform operations on a 2-megabyte contiguous block of memory, where the microcontroller employs the lookup table to translate each 2-megabyte contiguous address requested by the video decoder circuit to its appropriate page in the main memory. As soon as the video decoding operations are complete, the microcontroller releases the blocks of multiple pages of memory back for use by the computer.
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Citations
40 Claims
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1. In a computer system having a main memory, a storage device having encoded data stored therein and a processor controlled by an operating system, an electronic device comprising:
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a decoding circuit coupled to receive and decode the encoded data from the storage device; and a control circuit coupled to the decoding circuit, the processor and the main memory, the control circuit being configured to request continuous use of several portions of the main memory from the operating system, the portions of the main memory having noncontiguous addresses, and being configured to translate the noncontiguous addresses to contiguous addresses of a block of memory, and wherein the decoding circuit is configured to request at least some of the contiguous addresses of the block of memory, and wherein the control circuit translates the requested contiguous addresses of the block of memory to requested noncontiguous addresses and permits the decoding circuit to access the portions of the main memory. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. In a computer system controlled by an operating system and having a main memory, an electronic device comprising:
a control circuit coupled to the processor and the main memory, the control circuit being configured to request continuous use of several portions of the main memory from the operating system, the memory portions having noncontiguous addresses, and being configured to translate the noncontiguous addresses to contiguous addresses of a block of memory, wherein the control circuit permits access to the portions of the main memory as the block of memory based on the contiguous addresses. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18)
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19. A computer system, comprising:
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a main memory; a storage device having encoded data stored therein; a processor coupled to the main memory and the storage device and controlled by an operating system; and a control circuit coupled to the processor and the main memory, the control circuit being configured to request continuous use of several portions of the main memory from the operating system, the memory portions having noncontiguous addresses, and being configured to translate the noncontiguous addresses to contiguous addresses of a block of memory, wherein the control circuit permits access to the portions of the main memory through the block of memory based on the contiguous addresses. - View Dependent Claims (20, 21, 22, 23, 24)
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25. In a computer system having a processor controlled by an operating system and having a main memory, a storage device having encoded data stored therein, a decoding circuit coupled to receive and decode the encoded data from the storage device, and a control circuit coupled to the decoding circuit, the processor, and the main memory, the control circuit using a memory management method comprising the steps of:
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requesting contiguous use of several portions of the main memory from the operating system, the portions of the main memory having noncontiguous addresses; translating the noncontiguous addresses to contiguous addresses of a block of memory; receiving requests for access to a block of memory from the decoding circuit; translating the contiguous addresses to the noncontiguous addresses; and providing access to the portions of the main memory as the block of memory for the decoding circuit. - View Dependent Claims (26, 27, 28, 29, 30, 31)
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32. In a computer system having a processor controlled by an operating system, having a main memory and a control circuit using a memory management method comprising the steps of:
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requesting continuous use of several portions of the main memory from the operating system, the portions of the main memory having noncontiguous addresses; translating the noncontiguous addresses to contiguous addresses of a block of memory; receiving requests for access to a block of memory; and translating the contiguous addresses to the noncontiguous addresses. - View Dependent Claims (33, 34, 35, 36, 37, 38, 39, 40)
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Specification