Data processing apparatus and method for pre-fetching an instruction in to an instruction cache
First Claim
1. A data processing apparatus for fetching an instruction in to an instruction cache, comprising:
- an instruction cache for storing instructions;
a processor core arranged, when an instruction is required by the processor core, to output an instruction address to the instruction cache on an instruction address bus, and to issue a predetermined control signal to the instruction cache to cause the instruction cache to perform an instruction fetch procedure, the processor core arranged to receive the instruction corresponding to that instruction address on an instruction data bus only when said processor core issues said predetermined control signal;
a coprocessor arranged, when an instruction is to be added to the instruction cache without the instruction being received by the processor core, to execute a first predetermined instruction also executed by the processor core, the first predetermined instruction causing the coprocessor to also issue a predetermined control signal to the instruction cache, and causing the processor core to output to the instruction cache the instruction address data for the instruction to be added to the instruction cache without issuing the processor core originated predetermined control signal;
the instruction cache being responsive to the coprocessor originated predetermined control signal and the instruction address from the processor core to perform the instruction fetch procedure, and, if this results in a cache miss, to cause the retrieval of the instruction from memory for storage in the instruction cache, the processor core ignoring the retrieved instruction.
3 Assignments
0 Petitions
Accused Products
Abstract
The present invention provides a data processing apparatus for fetching an instruction in to an instruction cache, comprising an instruction cache for storing instructions, and a processor core for outputting an instruction address to the instruction cache on an instruction address bus, and for receiving the instruction corresponding to that instruction address on an instruction data bus The processor core is arranged to issue a predetermined control signal to the instruction cache when outputting the instruction address to cause the instruction cache to perform an instruction fetch procedure. In accordance with the present invention, a coprocessor is provided for executing a first predetermined instruction also executed by the processor core, the first predetermined instruction causing the coprocessor to issue the predetermined control signal to the instruction cache, and causing the processor core to output to the instruction cache the instruction address data for an instruction to be added to the instruction cache without issuing the predetermined control signal. Further, the instruction cache is responsive to the predetermined control signal from the coprocessor and the instruction address from the processor core to perform the instruction fetch procedure, and, if this results in a cache miss, to cause the retrieval of the instruction from memory for storage in the instruction cache, the processor core being arranged to ignore the retrieved instruction. The above approach allows an instruction to be pre-fetched and stored in the instruction cache without that instruction being returned to the processor core for execution, and without any additional logic needing to be added to the instruction cache to support pre-fetching.
57 Citations
16 Claims
-
1. A data processing apparatus for fetching an instruction in to an instruction cache, comprising:
-
an instruction cache for storing instructions; a processor core arranged, when an instruction is required by the processor core, to output an instruction address to the instruction cache on an instruction address bus, and to issue a predetermined control signal to the instruction cache to cause the instruction cache to perform an instruction fetch procedure, the processor core arranged to receive the instruction corresponding to that instruction address on an instruction data bus only when said processor core issues said predetermined control signal; a coprocessor arranged, when an instruction is to be added to the instruction cache without the instruction being received by the processor core, to execute a first predetermined instruction also executed by the processor core, the first predetermined instruction causing the coprocessor to also issue a predetermined control signal to the instruction cache, and causing the processor core to output to the instruction cache the instruction address data for the instruction to be added to the instruction cache without issuing the processor core originated predetermined control signal; the instruction cache being responsive to the coprocessor originated predetermined control signal and the instruction address from the processor core to perform the instruction fetch procedure, and, if this results in a cache miss, to cause the retrieval of the instruction from memory for storage in the instruction cache, the processor core ignoring the retrieved instruction. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
-
-
14. A method of operating a data processing apparatus to fetch an instruction in to an instruction cache, comprising the steps of:
-
outputting from a processor core an instruction address to the instruction cache on an instruction address bus; outputting, when an instruction is required by the processor core, from the processor core a predetermined control signal to the instruction cache while outputting the instruction address to cause the instruction cache to perform an instruction fetch procedure; receiving at the processor core on an instruction data bus the instruction corresponding to the instruction address only when the processor core has issued said predetermined control signal; arranging, when an instruction is to be added to the instruction cache without the instruction being received by the processor core, a coprocessor and the processor core to execute a first predetermined instruction, the first predetermined instruction causing the coprocessor to issue a predetermined control signal to the instruction cache, and causing the processor core to output to the instruction cache the instruction address data for the instruction to be added to the instruction cache without issuing the processor core originated predetermined control signal; arranging the instruction cache to perform the instruction fetch procedure in response to the predetermined control signal from the coprocessor and the instruction address from the processor core; if the instruction fetch procedure results in a cache miss, retrieving the instruction from memory for storage in the instruction cache, the processor core being arranged to ignore the retrieved instruction. - View Dependent Claims (15, 16)
-
Specification