Method for attachment or integration of a BIOS device into a computer system using the system memory address and data bus

• US 5,961,643 A
• Filed: 09/30/1997
• Issued: 10/05/1999
• Est. Priority Date: 09/30/1997
• Status: Expired due to Term

• Current Assignee: Mei California, Inc. (Micron Technology, Inc.)
• Original Assignee: Micro Electronics Incorporated
• Inventors: Klein, Dean A.
• Primary Examiner(s): Heckler, Thomas M.
• Application Number:
  US08/941,664
• Time in Patent Office: 735 Days
• Field of Search: 395/652, 713/2
• US Class Current: 713/2
• CPC Class Codes: G06F 9/4403 Processor initialisation

Abstract

Chipset or core logic for attachment of the ROM BIOS within the system architecture. Although normally attached to the ISA bus, the ROM BIOS may be attached to an alternate bus (e.g., the memory bus) located within the system, thereby potentially eliminating the ISA bus from the computer system.

Claims

1. A method of accessing a BIOS device in a computer system having a central processing unit, a core logic, a memory bus that can operate in a normal mode, and a BIOS device on the memory bus, the method comprising the acts of:

in the core logic, decoding signals on the memory bus;

if a BIOS access is desired, preventing the memory bus form operating in a normal mode;

presenting an address to the BIOS device by having the core logic place the address on the memory bus;

in the core logic, receiving data stored in the BIOS device at the address by sampling a portion of the memory bus;

transferring the data to the central processing unit; and

then operating the memory bus in a normal mode.

2. The method of claim 1, further comprising the act of sequencing a plurality of low-order bits on the address so that data from more than one addressable location is read from the BIOS device before the data is transferred to the central processing unit.

3. The method of claim 2, further comprising the act of transferring at least some of the contents of the BIOS device to faster memory at system start-up.

4. A method of executing BIOS instructions in a computer system having a memory bus with address lines and data lines, a BIOS device that is attached to the memory bus and that has BIOS instructions stored therein, a central processing unit, and a core logic, wherein the memory bus normally operates in a first mode, the method comprising the acts of:

bypassing the first mode of operation;

having the core logic place the address of the BIOS device on the memory bus, wherein the address occupies some of the data lines on the memory bus so that the address is presented to the BIOS device;

waiting for the BIOS device to place the addressed data on the memory bus;

reading the addressed data from the BIOS device by sampling a different set of data lines on the memory bus;

transferring the data from the BIOS device to the central processing unit; and

returning to the first mode of operation.

5. The method of claim 4, further comprising the act of sequencing a plurality of low-order bits on the address presented to the BIOS device so that data from more than one addressable location is read from the BIOS device before the data is transferred to the central processing unit.

6. The method of claim 5, further comprising the act of transferring at least some of the contents of the BIOS device to faster memory at system start-up.

7. The method of claim 6, further comprising the acts of:

communicating a portion of the address presented to the BIOS device by the core logic to the BIOS device over the memory address lines, and

communicating another portion of the address to the BIOS device over the memory data lines.

8. The method of claim 7, further comprising the act of presenting the entire address to the BIOS device over the memory address lines.

9. In a logic device for controlling BIOS operations in a computer system having a memory bus with address lines and data lines, a BIOS device that is attached to the memory bus and that has BIOS instructions stored therein, a central processing unit, and a core logic, wherein the memory bus normally operates in a first mode, a method comprising the acts of:

in the core logic, decoding signals on the memory bus;

if a BIOS access is desired, preventing the memory bus from operating in the first mode;

waiting for previously-initiated operations on the memory bus to complete;

presenting an address to the BIOS device by having the core logic place the address on the memory bus,

in the core logic, receiving data stored in the BIOS device at the address by sampling a portion of the memory bus,

transferring the data to the central processing unit; and

returning to the first mode of operation.

10. The method of claim 9, further comprising the act of sequencing a plurality of low-order bits on the address so that data from more than one addressable location is read from the BIOS device before the data is transferred to the central processing unit.

11. The method of claim 10, further comprising the act of transferring at least some of the contents of the BIOS device to faster memory at system start-up.

12. The method of claim 11, wherein the act of presenting an address to the BIOS device, and the act of receiving data involve data transfers on different portions of the memory bus.

13. The method of claim 12, further comprising the acts of:

communicating a portion of the address presented to the BIOS device by the core logic to the BIOS device over the memory address lines, and

communicating another portion of the address to the BIOS device over the memory data lines.

14. The method of claim 13, wherein the act of presenting an address to the BIOS device includes the act of presenting an address to a non-volatile, electrically-erasable, programmable read-only memory device.

15. The method of claim 14, wherein the act of receiving data stored in the BIOS device includes the act of receiving eight-bit data units that are stored in an eighteen-bit address space within the non-volatile, electrically-erasable, programmable read-only memory device.