Semiconductor CMOS device with circuit for preventing latch-up
First Claim
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1. A semiconductor device including a substrate bias generating circuit for generating a substrate bias for a semiconductor substrate of a first conductive type, a CMOS circuit formed on the semiconductor substrate, and a first protection circuit formed on the semiconductor substrate for preventing a latch-up from occurring in the CMOS circuit, the first protection circuit comprising:
- a first diffusion region of a second conductive type having a first perimeter and formed on the substrate;
a second diffusion region of the second conductive type doped more than said first diffusion region, said second diffusion region being formed in said first diffusion region and electrically coupled with a first power supply having a first potential;
a third diffusion region of the first conductive type formed apart from said second diffusion region in said first diffusion region, and electrically coupled with an input line; and
a fourth diffusion region of the second conductive type formed on the substrate, said fourth diffusion region having a fourth perimeter spaced apart from the first perimeter of said first diffusion region and electrically coupled with a second power supply having a second potential different from the first potential of the first power supply;
wherein the substrate is electrically coupled with the substrate bias generating circuit outside of the fist protection circuit.
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Abstract
A semiconductor device has a substrate bias generating circuit for generating a substrate bias to be applied to a p-type semiconductor substrate, a CMOS circuit formed on the semiconductor substrate, and a latch-up protection circuit. The latch-up protection circuit has an n-type first region, a highly doped n-type second region, a p-type third region apart from the second region, in the first region and an n-type fourth region surrounding said first region formed apart from the first region on the surface of the substrate. The second region is coupled with a power supply Vcc, the third region is coupled with an input line, the fourth region is coupled with a ground Vss, and the substrate is coupled with the substrate bias generating circuit.
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Citations
13 Claims
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1. A semiconductor device including a substrate bias generating circuit for generating a substrate bias for a semiconductor substrate of a first conductive type, a CMOS circuit formed on the semiconductor substrate, and a first protection circuit formed on the semiconductor substrate for preventing a latch-up from occurring in the CMOS circuit, the first protection circuit comprising:
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a first diffusion region of a second conductive type having a first perimeter and formed on the substrate; a second diffusion region of the second conductive type doped more than said first diffusion region, said second diffusion region being formed in said first diffusion region and electrically coupled with a first power supply having a first potential; a third diffusion region of the first conductive type formed apart from said second diffusion region in said first diffusion region, and electrically coupled with an input line; and a fourth diffusion region of the second conductive type formed on the substrate, said fourth diffusion region having a fourth perimeter spaced apart from the first perimeter of said first diffusion region and electrically coupled with a second power supply having a second potential different from the first potential of the first power supply; wherein the substrate is electrically coupled with the substrate bias generating circuit outside of the fist protection circuit. - View Dependent Claims (2, 3, 4, 5, 10, 11)
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6. A semiconductor device including a semiconductor substrate of a first conductive type, a substrate bias generating circuit for generating a substrate bias for the semiconductor substrate, a CMOS circuit formed on the semiconductor substrate, a semiconductor controlled rectifier device for preventing a latch-up from occurring in the CMOS circuit, and a second protection circuit for preventing electrostatic breakdown from occurring in the CMOS circuit, the semiconductor controlled rectifier device comprising:
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a first diffusion region of a second conductive type having a first perimeter, said first diffusion region being formed on the substrate and electrically coupled with a first power supply having a first potential; a second diffusion region of the first conductive type formed in said first diffusion region and electrically coupled with an input line; a third diffusion region of the second conductive type formed in the substrate, said third diffusion region having a third perimeter spaced apart from the first perimeter of said first diffusion region and electrically coupled with a second power supply having a second potential different from the first potential of the first power supply; and an electrode formed on the substrate, except on said first, second, and third diffusion regions, and electrically coupling the substrate with the substrate bias generating circuit. - View Dependent Claims (7, 8, 9, 12, 13)
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Specification
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Current AssigneeOki Semiconductor Company Limited (ROHM Co., Ltd.)
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Original AssigneeOKI Electric Industry Company Limited
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InventorsKikuchi, Hidekazu, Kato, Katsuhiro
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Primary Examiner(s)Thomas, Tom
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Assistant Examiner(s)Abraham, Fetsum
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Application NumberUS08/915,325Time in Patent Office776 DaysField of Search257/355-360, 257/372, 257/328, 257/173, 257/174, 327/91, 327/94, 327/428US Class Current257/372CPC Class CodesH01L 27/0218 of field effect structuresH01L 27/0921 Means for preventing a bipo...
