Method for programming complex PLD having more than one function block type

• US 5,963,048 A
• Filed: 03/12/1997
• Issued: 10/05/1999
• Est. Priority Date: 12/23/1994
• Status: Expired due to Term

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.), Tetra Laval Holdings & Finance SA (Tetra Laval Holdings BV)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Silver, Joshua M., Harrison, David A., Soe, Soren T.
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): Kazimi, Hani M.
• Application Number:
  US08/818,138
• Time in Patent Office: 937 Days
• Field of Search: 395/500, 364/488-491, 326/37-40, 326/44, 326/47, 340/825.79, 340/825.83, 711/202
• US Class Current: 326/39
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]

Abstract

A method for programming programmable logic devices (PLDs) having multiple function block types to implement a logic function, whereby the logic function is mapped into one of the function block types before being mapped into the remaining function block types. In one embodiment, a PLD containing both "fast" function blocks (FFBs) and "high density" function blocks (HDFBs) are programmed such that the FFBs are programmed prior to the HDFBs. This method maximizes the overall speed of an implemented logic function.

Claims

1. A computer implemented method for configuring a programmable logic device to implement a logic function, the programmable logic device including a first type of function block and a second type of function block the method comprising the steps of:

mapping portions of the logic function into the first type of function block providing a first speed and into the second type of function block providing a second speed, wherein the first speed is greater than the second speed;

identifying portions of the logic function which are not mapped in the first type of function block and which qualify for implementation in the first type of function block; and

if the first type of function block includes sufficient unassigned resources to implement a selected identified qualified portion, then mapping the selected identified qualified portion into the first type of function block.

2. The method of claim 1, wherein the step of identifying includes assigning a weight value to each identified qualified portion, and the step of attempting includes selecting the identified qualified portion having a highest weight value.

3. The method of claim 2, wherein the step of attempting further comprises splitting the selected identified qualified portion into two or more sub-portions which are mappable into available resources into a single function block of the first type of function blocks.

4. The method of claim 1, wherein the step of mapping comprises the steps of:

identifying portions of the logic function which qualify for implementation in the first type of function block, wherein said first type of function block provides a first density;

splitting the qualified portions of said logic function into a plurality of sub-portions such that each sub-portion is implementable in said first type of function block;

mapping the identified qualified portions of the logic function into the first type of function block until the first type of function block is fully utilized; and

mapping unmapped qualified portions of the logic function into the second type of function block, wherein the second type of function block provides a second density, the second density being greater than the first density.

5. The method of claim 4, wherein the step of mapping the identified qualified portions of the logic function into the first type of function block comprises mapping pre-designated qualified portions of the logic function before mapping un-designated qualified portions of the logic function.

6. The method of claim 1, wherein the step of identifying portions of the logic function further comprises identifying function blocks of the first type of function block containing unused resources, and wherein the step of attempting to map further comprises attempting to map the identified qualified portions of the logic function into the identified function blocks.

7. The method of claim 6, wherein the step of attempting to map is performed until the first type of function block is fully utilized, and wherein the method further comprises the step of mapping any remaining identified qualified portions of the logic function into the second type of function block.

8. A computer implemented method for configuring a programmable logic device to implement a logic function, the programmable logic device including a first type of function block and a second type of function block, the method comprising the steps of:

mapping portions of the logic function into the first type of function block providing a first speed and into the second type of function block providing a second speed, wherein the first speed is greater than the second speed;

identifying portions of the logic function which are not mapped in the first type of function block and which qualify for implementation in the first type of function block;

mapping the identified qualified portions of the logic function into the first type of function block until the first type of function block is fully utilized; and

mapping any remaining identified qualified portions of the logic function into the second type of function block.

9. The method of claim 8, wherein the step of identifying includes assigning a weight value to each identified qualified portion, and the step of attempting includes selecting the identified qualified portion having a highest weight value.

10. The method of claim 9, wherein the step of attempting further comprises splitting the selected identified qualified portion into two or more sub-portions which are mappable into available resources into a single function block of the first type of function blocks.

11. The method of claim 8, wherein the step of mapping portions of the logic function into the first type of function block and into the second type of function block comprises the steps of:

identifying portions of the logic function which qualify for implementation in the first type of function block, wherein said first type of function block provides a first density;

splitting the qualified portions of said logic function into a plurality of sub-portions such that each sub-portion is implementable in said first type of function block;

mapping the identified qualified portions of the logic function into the first type of function block until the first type of function block is fully utilized; and

mapping unmapped qualified portions of the logic function into the second type of function block, wherein the second type of function block provides a second density, the second density being greater than the first density.

12. The method of claim 11, wherein the step of mapping the identified qualified portions of the logic function into the first type of function block comprises mapping pre-designated qualified portions of the logic function before mapping un-designated qualified portions of the logic function.

13. The method of claim 8, wherein the step of mapping the identified qualified resources into the first type of function block further comprises identifying function blocks of the first type of function block containing unused resources.

14. The method of claim 13, wherein each function block of the first type of function block contains a plurality of macrocells, and each of the identified function blocks contains two unused macrocells.

15. A computer implemented method for configuring a programmable logic device to implement a logic function, the programmable logic device including a first type of function block and a second type of function block, the method comprising the steps of:

mapping portions of the logic function into the first type of function block providing first speed and into the second type of function block providing a second speed, wherein the first speed is greater than the second speed;

identifying portions of the logic function which are mapped into the second type of function block and which qualify for implementation in the first type of function block;

unmapping the identified qualified portions from the second type of function block; and

mapping the unmapped identified qualified portions into the first type of function block.

16. The method of claim 15, wherein the step of identifying includes assigning a weight value to each identified qualified portion, and the step of attempting includes selecting the identified qualified portion having a highest weight value.

17. The method of claim 16, wherein the step of attempting further comprises splitting the selected identified qualified portion into two or more sub-portions which are mappable into available resources into a single function block of the first type of function blocks.

18. The method of claim 15, wherein the step of mapping portions of the logic function into the first type of function block and into the second type of function block comprises the steps of:

identifying portions of the logic function which qualify for implementation in the first type of function block, wherein said first type of function block provides a first density;

splitting the qualified portions of said logic function into a plurality of sub-portions such that each sub-portion is implementable in said first type of function block;

mapping the identified qualified portions of the logic function into the first type of function block until the first type of function block is fully utilized; and

mapping unmapped qualified portions of the logic function into the second type of function block, wherein the second type of function block provides a second density, the second density being greater than the first density.

19. The method of claim 15, further comprising the step of identifying function blocks of the first type of function block containing unused resources, wherein the step of mapping further comprises mapping the unmapped identified resources into the identified function blocks.

20. The method of claim 19, wherein each function block of the first type of function block contains a plurality of macrocells, and each of the identified function blocks contains two unused macrocells.