Self-biasing CMOS PECL receiver with wide common-mode range and multi-level-transmit to binary decoder
First Claim
1. A differential receiver for decoding binary-encoded or multi-level-encoded differential inputs, the differential receiver comprising:
- a pair of differential inputs including a first differential input and a second differential input, the pair of differential inputs receiving an input data stream encoded with binary data or encoded with multi-level-encoded data;
a reference-voltage generator for generating a binary reference-voltage and a multi-level reference-voltage;
a reference-voltage selector, coupled to the reference-voltage generator, for outputting the binary reference-voltage when the input data stream is encoded with binary data, and for outputting the multi-level reference-voltage when the input data stream contains the multi-level-encoded data, the reference-voltage selector outputting a reference-voltage;
a first differential comparator receiving the first differential input and receiving the reference voltage from the reference-voltage selector, for comparing a first voltage of the first differential input to the reference-voltage and outputting a first detection signal when the first voltage exceeds the reference-voltage;
a second differential comparator receiving the second differential input and receiving the reference voltage from the reference-voltage selector, for comparing a second voltage of the second differential input to the reference-voltage and outputting a second detection signal when the second voltage exceeds the reference-voltage; and
a decoder, receiving the first detection signal from the first differential comparator and receiving the second detection signal from the second differential comparator, for outputting a decoded binary data stream, the decoder outputting the first detection signal as the decoded binary data stream when the input data stream is encoded with binary data, but the decoder outputting as the decoded binary stream a logical combination of the first detection signal and the second detection signal when the input data stream contains the multi-level-encoded data,whereby a single reference-voltage is compared to the first differential input and to the second differential input to detect and decode multi-level-encoded data.
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Abstract
A pseudo-emitter-coupled-logic (PECL) receiver has a wide common-mode range. Two current-mirror CMOS differential amplifiers are used. One amplifier has n-channel differential transistors and a p-channel current mirror, while the second amplifier has p-channel differential transistors and an n-channel current mirror. When the input voltages approach power or ground, one type of differential transistor continues to operate even when the other type shuts off. The outputs of the two amplifiers are connected together and each amplifier receives the same differential input signals. The tail-current transistor is self-biased using the current-mirror'"'"'s gate-bias. This self biasing of each amplifier eliminates the need for an additional voltage reference and allows each amplifier to adjust its biasing over a wide input-voltage range. Thus the common-mode input range is extended using self biasing and complementary amplifiers. The complementary self-biased comparators can be used for receiving binary or multi-level-transition (MLT) inputs by selecting different voltage references for threshold comparison. Using the same reference on both differential inputs eliminates a second reference for multi-level inputs having three levels. Thus binary and MLT inputs can be detected and decoded by the same decoder.
73 Citations
12 Claims
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1. A differential receiver for decoding binary-encoded or multi-level-encoded differential inputs, the differential receiver comprising:
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a pair of differential inputs including a first differential input and a second differential input, the pair of differential inputs receiving an input data stream encoded with binary data or encoded with multi-level-encoded data; a reference-voltage generator for generating a binary reference-voltage and a multi-level reference-voltage; a reference-voltage selector, coupled to the reference-voltage generator, for outputting the binary reference-voltage when the input data stream is encoded with binary data, and for outputting the multi-level reference-voltage when the input data stream contains the multi-level-encoded data, the reference-voltage selector outputting a reference-voltage; a first differential comparator receiving the first differential input and receiving the reference voltage from the reference-voltage selector, for comparing a first voltage of the first differential input to the reference-voltage and outputting a first detection signal when the first voltage exceeds the reference-voltage; a second differential comparator receiving the second differential input and receiving the reference voltage from the reference-voltage selector, for comparing a second voltage of the second differential input to the reference-voltage and outputting a second detection signal when the second voltage exceeds the reference-voltage; and a decoder, receiving the first detection signal from the first differential comparator and receiving the second detection signal from the second differential comparator, for outputting a decoded binary data stream, the decoder outputting the first detection signal as the decoded binary data stream when the input data stream is encoded with binary data, but the decoder outputting as the decoded binary stream a logical combination of the first detection signal and the second detection signal when the input data stream contains the multi-level-encoded data, whereby a single reference-voltage is compared to the first differential input and to the second differential input to detect and decode multi-level-encoded data. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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Specification