Large scale integrated circuit having functional blocks controlled with clock signals that conduct setting operations at different times

• US 5,963,075 A
• Filed: 08/19/1997
• Issued: 10/05/1999
• Est. Priority Date: 08/19/1996
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Corporation
• Inventors: Hiiragizawa, Yasunori
• Primary Examiner(s): Callahan, Tim
• Assistant Examiner(s): KIM, JUNG H
• Application Number:
  US08/914,091
• Time in Patent Office: 777 Days
• Field of Search: 327/293, 327/295, 327/297, 327/565, 327/564, 327/296
• US Class Current: 327/295
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew

Abstract

An LSIC includes a clock distributor circuit capable of decreasing the power consumption and suppressing the deviation of the power source potential and the transient current. The circuit includes a plurality of functional blocks including CPU. The CPU conducts a data accessing operation via address and data buses to peripheral blocks. There is also provided a clock supply unit to supply clock signals in which at least one of the clock signals has a phase different from those of the remaining clock signals and the clock signals do not accomplish the setting operation at the same time.

Claims

1. A large scale integrated circuit (LSIC), comprising:

a plurality of functional blocks coupled with each other via an address bus, a data bus, and a plurality of control signals, at least one of the functional blocks being a control block for generating and outputting the control signals, the control block including means for conducting a data accessing operation to and from another one of the functional blocks via the address and data buses; and

clock supply means for respectively supplying the functional blocks with a plurality of clock signals,

wherein all of the plurality of clock signals ever conduct a setting operation at the same time.

2. An LSIC in accordance with claim 1, wherein the clock supply means includes a clock distributor circuit and at least one of the clock signals has a clock cycle different from those of the remaining clock signals.

3. An LSIC in accordance with claim 1, wherein the clock distributor circuit of the clock supply means includes three buffer circuits, two logical product circuits including a first logical product circuit and a second logical product circuit, and one flip-flop circuit,

the flip-flop circuit including a clock input terminal linked with a clock input signal,

the flip-flop circuit including a data output terminal connected to an input terminal of the first logical product circuit,

the flip-flop circuit including an inverted data output terminal coupled with an input terminal of the second logical product circuit and a data input terminal of the flip-flop circuit,

the first and second logical product circuits each including another input terminal connected to the clock input signal, and

the clock input signal and output terminals of the first and second logical product circuits being coupled respectively to the buffer circuits to a predetermined functional block of the LSIC.

4. An LSIC in accordance with claim 1, wherein two of the clock signals have the same frequency.

5. An LSIC in accordance with claim 4, wherein the two clock signals that have the same frequency have different phases.

6. An LSIC in accordance with claim 1, wherein two of the clock signals have the same pulse width but different phases.

7. An LSIC in accordance with claim 1, wherein two of the clock signals have the same frequency and pulse width.

8. An LSIC in accordance with claim 7, wherein the two clock signals that have the same frequency and pulse width have different phases.

9. A method of lowering power consumption in a large scale integrated circuit (LSIC) comprising the steps of supplying a plurality of clock signals to functional blocks of the LSIC, at least one of which is a control block for conducting data accessing operation to and from another one of the functional blocks, wherein two of the plurality of clock signals have different frequencies and all of the plurality of clock signals never conduct a setting operation at the same time.

10. The method according to claim 9, wherein two of the plurality of clock signals have the same frequency.

11. The method according to claim 10, wherein the two clock signals that have the same frequency have different phases.

12. The method according to claim 9, wherein two of the plurality of clock signals have the same pulse width but different phases.

13. The method according to claim 9, wherein two of the plurality of clock signals have the same frequency and pulse width but different phases.

14. A large scale integrated circuit (LSIC), comprising:

a plurality of functional blocks coupled with each other via an address bus, a data bus, and a plurality of control signals, at least one of the functional blocks being a control block for generating and outputting the control signals, the control block including means for conducting a data accessing operation to and from another one of the functional blocks via the address and data buses; and

clock supply means for respectively supplying the functional blocks with a plurality of clock signals,

wherein the clock supply means includes a clock distributor circuit and at least one of the clock signals has a clock cycle different from those of the remaining clock signals, and the clock distributor circuit includes three buffer circuits, two logical product circuits including a first logical product circuit and a second logical product circuit, and one flip-flop circuit,

the flip-flop circuit including a clock input terminal linked with a clock input signal,

the flip-flop circuit including a data output terminal connected to an input terminal of the first logical product circuit,

the flip-flop circuit including an inverted data output terminal coupled with an input terminal of the second logical product circuit and a data input terminal of the flip-flop circuit,

the first and second logical product circuits each including another input terminal connected to the clock input signal, and

the clock input signal and output terminals of the first and second logical product circuits being coupled respectively to the buffer circuits.

15. An LSIC according to claim 14, wherein all of said at least three clock output signals never conduct a setting operation at the same time.

16. An LSIC according to claim 14, wherein two of the clock output signals have the same frequency, but different phases.

17. An LSIC according to claim 14, wherein two of the clock output signals have the same pulse width but different phases.

18. An LSIC according to claim 14, wherein two of the clock output signals have the same frequency and pulse width, but different phases.