Display apparatus with digital output palette

• US 5,963,193 A
• Filed: 10/15/1996
• Issued: 10/05/1999
• Est. Priority Date: 02/05/1996
• Status: Expired due to Term

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Knox, Andrew, Pietrzak, Christopher Carlo
• Primary Examiner(s): Hjerpe, Richard A.
• Assistant Examiner(s): NGUYEN, FRANCIS N
• Application Number:
  US08/732,804
• Time in Patent Office: 1,085 Days
• Field of Search: 345/150, 345/139, 345/523, 345/119, 345/100, 345/94, 345/198, 345/211, 345/213, 345/507, 345/509, 345/197, 345/513, 348/615
• US Class Current: 345/601
• CPC Class Codes: G09G 2340/04 Changes in size, position or resolution of an image
• CPC Class Codes: G09G 2360/02 Graphics controller able to handle multiple formats, e.g. input or output formats
• CPC Class Codes: G09G 2370/04 Exchange of auxiliary data, i.e. other than image data, between monitor and graphics controller
• CPC Class Codes: G09G 2370/042 for monitor identification
• CPC Class Codes: G09G 5/006 Details of the interface to the display terminal specific for a display terminal using a CRT G09G1/167; using a flat panel G09G3/2096; circuits for interfacing with colour displays G09G5/04

Abstract

A display system comprises a digital video source coupled to a digital display device via an digital interface having a timing channel for carrying a pixel clock signal from the video source to the display device and a digital video channel for carrying a digital video bit stream from the video source to the display device. The video source comprises a pixel clock generator for generating the pixel clock signal, palette logic for outputting a pixel word on each pulse of the pixel clock signal, shift clock logic for multiplying the pixel clock signal by the number of bits in the pixel word to produce a shift clock signal, and serialiser logic for serially outputting the pixel word in the serial bit stream at the shift clock signal rate. The display device comprises a display screen for producing a pixel of an image in response to the pixel word; shift clock generator logic for multiplying the pixel clock signal by the number of bits in the pixel word, and deserialiser logic for receiving the input video bit stream at the shift clock signal rate to re-generate the pixel word from the video bit stream.

Claims

1. Data processing apparatus for generating serial video bit stream in the form of pulsed pixel data words, comprising:

a pixel clock generator for generating a pixel clock signal;

palette logic for generating a pixel data word on each pulse of the pixel clock signal;

shift clock generator logic for multiplying the pixel clock signal by the number of bits in the pixel data word to produce a shift clock signal; and

serialiser logic for outputting the pixel data word in a serial bit stream at the shift clock signal rate.

2. The data processing apparatus as defined in claim 1, further comprising control logic connected to the shift clock generator logic for reading the number of bits in the pixel data word from an external source.

3. The data processing apparatus as defined in claim 1, comprising cross-point switch logic for transferring the pixel data word generated by the palette logic to the serialiser logic.

4. The data processing apparatus as defined in claim 1, comprising error logic for generating an error code corresponding to the pixel data word and for adding the error code to the serial bit stream.

5. The data processing apparatus as defined in claim 2, comprising cross-point switch logic for transferring the pixel data word generated by the palette logic to the serialiser logic.

6. A digital display data processing apparatus comprising:

a display screen for producing a pixel of an image in response to a pixel word;

a timing receiver for receiving a pixel clock signal from an external video source;

shift clock generator logic for multiplying the pixel clock signal by the number of bits in the pixel word to produce a shift clock signal; and

deserialiser logic for receiving an input video bit stream at the shift clock signal rate to generate the pixel word.

7. The digital display data processing apparatus as defined in claim 6, comprising control logic connected to the shift clock generator logic for reading the number of bits in the pixel data word from an external source.

8. The digital display data processing an apparatus as defined in claim 6, comprising error logic for detecting an error in the pixel word and from an error code in the serial bit stream.

9. The digital display data processing apparatus as defined in claim 6, wherein the pixel word defines a pixel of a monochrome video image.

10. The digital display data processing apparatus as defined in claim 7, comprising error logic for detecting an error in the pixel word and from an error code in the serial bit stream.

11. The digital display data processing apparatus as defined claim 6, wherein the pixel word defines a colour component of a pixel of a colour video image.

12. A data processing display system, comprising:

a digital video source coupled to a digital display device through a digital interface having a timing channel for carrying a pixel clock signal from the digital video source to the digital display device and a digital video channel for carrying a digital video bit stream from the digital video source to the digital display device, wherein the digital video source includes a pixel clock generator for generating the pixel clock signal, palette logic for outputting a pixel word on each pulse of the pixel clock signal, first shift clock logic for multiplying the pixel clock signal by the number of bits in the pixel word to produce a shift clock signal, and serialiser logic for serially outputting the pixel word in the serial bit stream at the shift clock signal rate, and wherein the digital display device includes a display screen for producing a pixel of an image in response to the pixel word, second shift clock logic for multiplying the pixel clock signal by the number of bits in the pixel word, and deserialiser logic for receiving the input video bit stream at the shift clock signal rate to re-generate the pixel word from the video bit stream.

13. The data processing display system, as defined in claim 12, wherein the interface comprises a control channel for communicating the number of bits in the pixel word from the digital video source to the digital display device.

14. A computer system comprising.

a processor;

a memory; and

a display system including a digital video source coupled to a digital display device through a digital interface having a timing channel for carrying a pixel clock signal from the digital video source to the digital display device, and a digital video channel for carrying a digital video bit stream from the digital video source to the digital display device, wherein the digital video source includes a pixel clock generator for generating the pixel clock signal, palette logic for outputting a pixel word on each pulse of the pixel clock signal, first shift clock logic for multiplying the pixel clock signal by the number of bits in the pixel word to produce a shift clock signal, and serialiser logic for serially outputting the pixel word in the digital video bit stream at the shift clock signal rate, and wherein the digital display device includes a display screen for producing a pixel of an image in response to the pixel word, second shift clock logic for multiplying the pixel clock signal by the number of bits in the pixel word, and deserialiser logic for receiving the serially outputted pixel word in the digital video bit stream from the serialiser logic at the shift clock signal rate to re-generate the pixel word from the digital video bit stream.