Video frame synchronization of independent timing generators for frame buffers in a master-slave configuration

• US 5,963,200 A
• Filed: 08/20/1997
• Issued: 10/05/1999
• Est. Priority Date: 03/21/1995
• Status: Expired due to Term

• Current Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Deering, Michael F., Lavelle, Michael G., Kehlet, David C., Koltzoff, Alex N.
• Primary Examiner(s): Tung, Kee M.
• Application Number:
  US08/914,973
• Time in Patent Office: 776 Days
• Field of Search: 345/213, 345/504, 345/501, 345/1, 345/8, 345/9, 345/507-509, 348/51-53, 348/524, 365/189.25, 370/17
• US Class Current: 345/213
• CPC Class Codes: G06F 3/1446 display composed of modules, e.g. video walls
• CPC Class Codes: G06F 3/1454 involving copying of the display data of a local workstation or window to a remote workstation or window so that an actual copy of the data is displayed simultaneously on two or more displays, e.g. teledisplay
• CPC Class Codes: G09G 2310/0224 Details of interlacing
• CPC Class Codes: G09G 2360/04 Display device controller operating with a plurality of display units
• CPC Class Codes: G09G 5/06 using colour palettes, e.g. look-up tables
• CPC Class Codes: G09G 5/08 Cursor circuits
• CPC Class Codes: G09G 5/12 Synchronisation between the display unit and other units, e.g. other display units, video-disc players
• CPC Class Codes: G09G 5/18 Timing circuits for raster scan displays specially adapted for television H04N ; synchronisation between the display unit and other display units, videodisc player G09G5/12
• CPC Class Codes: H04N 13/161 Encoding, multiplexing or demultiplexing different image signal components for multi-view video sequence encoding H04N19/597
• CPC Class Codes: H04N 13/167 Synchronising or controlling image signals
• CPC Class Codes: H04N 13/189 Recording image signals; Reproducing recorded image signals
• CPC Class Codes: H04N 13/332 Displays for viewing with the aid of special glasses or head-mounted displays [HMD]
• CPC Class Codes: H04N 13/398 Synchronisation thereof; Control thereof

Abstract

A method and apparatus for synchronizing the vertical blanking of multiple frame buffers which may exist on the same computer or separate computers for certain applications including stereo display, virtual reality and video recording, which require such synchronization. To obtain the required synchronization one frame buffer is designation as the master. It provides a signal called FIELD that changes state (0 to 1 or 1 to 0) at the start of every vertical sync event on the master frame buffer. All other frame buffers are set to be slaves. Their timing generators sample the master'"'"'s FIELD signal. When they detect the master'"'"'s FIELD signal changing state, they set their own internal timing to match to thereby achieve frame synchronization.

Claims

1. An apparatus for synchronizing a vertical blanking signal for each of a plurality of independent frame buffers comprising:

a plurality of RAMDACs, each for coupling to a corresponding rendering controller and a display monitor which receives video signals, wherein one of said plurality of RAMDACs operates as a master and each of the other of said plurality of RAMDACs operates as a slave, each of said RAMDACS including logic which generates a vertical blanking signal, each of said slave RAMDACs including reset logic which generates a signal which resets said vertical blanking signal logic;

wherein said RAMDAC operating as a master further comprises a field signal generator which generates a field signal which is provided to each of said plurality of RAMDACs operating as a slave, and each of said slave RAMDACs upon receipt of said field signal operates said reset logic to thereby synchronize the video signals provided to its corresponding display monitor.

2. The apparatus defined by claim 1 wherein said logic which generates said vertical blanking signal comprises:

a vertical counter which is incremented at each leading edge of an internal HSYNC* signal.

3. The apparatus defined by claim 2 wherein:

said vertical blanking signal is asserted during an even field when the vertical counter is an odd number greater than or equal to a value stored in a horizontal blank assertion point register and during an odd field when the vertical counter is an even number greater than or equal to a value stored in the horizontal blank assertion point register; and

said vertical blanking signal is deasserted during an even field when the vertical counter is an even number greater than a value stored in a horizontal blank negation point register and during an odd field when the vertical counter is an odd number greater than a value stored in the horizontal blank negation point register.

4. The apparatus defined by claim 2 wherein said reset logic comprises a circuit which receives said field signal as an input and processes said received field signal to generate a field reset signal.

5. The apparatus defined by claim 2 wherein said reset logic circuit comprises:

a) a first flip-flop which receives said field signal as an input;

b) a second flip-flop coupled to an output of said first flip-flop;

c) a third flip-flop coupled to an output of said second flip-flop;

d) an XOR gate coupled to an output of said third flip-flop;

e) a multiplexor having one input coupled to an output of said XOR gate and a second input coupled to an output of an edge discriminator.

6. The apparatus defined by claim 1 wherein said field signal generator comprises:

a) a comparator;

b) a first flip-flop coupled to an output of said comparator;

c) a second flip-flop coupled to an output of said first flip-flop;

d) an AND gate coupled to an output of said second flip-flop;

e) a third flip-flop coupled to an output of said AND gate;

f) a tri-state driver coupled to an output of said third flip-flop.

7. The apparatus defined by claim 1 further comprising:

a) a set of registers including a VSAP (Vertical Sync Assertion Point) register, a VSNP (Vertical Sync Negation Point) register, an EIAP (Equalization Interval Assertion Point) register, an EINP (Equalization Interval Negation Point) register, a VBAP (Vertical Blank Assertion Point) register, and a VBNP (Vertical Blank Negation Point) register;

b) horizontal and vertical counters coupled to said set of registers and said field signal generator;

c) equality comparators coupled to said horizontal and vertical counters and said set of registers; and

d) event registers coupled to said equality comparators and said set of registers.

8. The apparatus defined by claim 7 wherein said set of registers further comprises a HSNP (Horizontal Sync Negation Point) register, a HBNP (Horizontal Blank Negation Point) register, a HBAP (Horizontal Blank Assertion Point) register, and a HSAP (Horizontal Sync Assertion Point) register containing values having the relationship O<

HSNP<

HBNP<

HBAP<

HSAP.

9. The apparatus defined by claim 7 wherein the VSNP, EINP, VBNP, VBAP, EIAP and VSAP registers contain values having the relationship O<

VSNP<

EINP<

VBNP<

VBAP≦

EIAP≦

VSAP.

10. A method for synchronizing a vertical blanking signal for each of a plurality of independent frame buffers comprising the steps of:

a) designating one of a plurality of RAMDACs, each for coupling to a corresponding rendering controller and a display monitor which receives video signals, as a master and designating each of the other of said plurality of RAMDACs as a slave;

b) generating a vertical blanking signal for each of said plurality of independent frame buffers;

c) synchronizing the video signals provided to the display monitor coupled to each of said plurality of RAMDACs by generating a field signal which is provided to each of said plurality at RAMDACs operating as a slave, said slave RAMDACs, upon receipt of said field signal, operating to reset logic used for generating the vertical blanking signal to thereby synchronize the video signals to be provided to its corresponding display monitor.

11. The method defined by claim 10 wherein said vertical blanking signal generating step comprises the step of;

incrementing a vertical counter at each leading edge of an internal HSYNC* signal.

12. The method defined by claim 11 wherein:

said vertical blanking signal is asserted during an even field when the vertical counter is an odd number greater than or equal to a value stored in a horizontal blank assertion point register and during an odd field when the vertical counter is an even number greater than or equal to a value stored in the horizontal blank assertion point register; and

said vertical blanking signal is deasserted during an even field when the vertical counter is an even number greater than a value stored in a horizontal blank negation point register and during an odd field when the vertical counter is an odd number greater than a value stored in the horizontal blank negation point register.

13. The method defined by claim 10 wherein said operating to reset logic step comprises the steps of:

a) receiving said field signal as an input; and

b) processing said received field signal to generate a field reset signal.