Multi-format reduced memory MPEG decoder with hybrid memory address generation

• US 5,963,222 A
• Filed: 01/28/1998
• Issued: 10/05/1999
• Est. Priority Date: 10/27/1997
• Status: Expired due to Term

• Current Assignee: MediaTek, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Ciacelli, Mark L., Cheney, Dennis P., Ngai, Chuck H.
• Primary Examiner(s): Tung, Kee M.
• Application Number:
  US09/014,896
• Time in Patent Office: 615 Days
• Field of Search: 345/516, 345/202, 345/501, 345/203, 345/515, 345/513, 345/517, 345/521, 382/232, 382/244-246, 382/248, 382/250, 382/251, 348/402, 348/403, 348/405, 348/407, 348/413, 348/416-418, 348/384, 348/390, 348/395, 348/400, 348/714
• US Class Current: 345/572
• CPC Class Codes: H04N 11/20 Conversion of the manner in which the individual colour picture signal components are combined, e.g. conversion of colour television standards
• CPC Class Codes: H04N 19/186 the unit being a colour or a chrominance component
• CPC Class Codes: H04N 19/423 characterised by memory arrangements H04N19/433 takes precedence
• CPC Class Codes: H04N 19/427 Display on the fly, e.g. simultaneous writing to and reading from decoding memory
• CPC Class Codes: H04N 19/428 Recompression, e.g. by spatial or temporal decimation
• CPC Class Codes: H04N 19/433 characterised by techniques for memory access
• CPC Class Codes: H04N 19/577 Motion compensation with bidirectional frame interpolation, i.e. using B-pictures
• CPC Class Codes: H04N 19/59 involving spatial sub-sampling or interpolation, e.g. alteration of picture size or resolution
• CPC Class Codes: H04N 19/61 in combination with predictive coding
• CPC Class Codes: H04N 19/80 Details of filtering operations specially adapted for video compression, e.g. for pixel interpolation H04N19/635, H04N19/86 take precedence
• CPC Class Codes: H04N 21/426 Internal components of the client ; Characteristics thereof H04N5/44 takes precedence
• CPC Class Codes: H04N 21/4435 Memory management allocation of memory to service a request G06F9/5016; addressing or allocating within memory systems or architectures G06F12/02
• CPC Class Codes: H04N 7/0122 the input and the output signals having different aspect ratios
• CPC Class Codes: H04N 9/64 Circuits for processing colour signals H04N9/77 takes precedence; camera processing pipelines for processing colour signals H04N23/84

Abstract

An address generation engine is disclosed for a digital video decoder unit coupled to memory in a digital video decoder system wherein the memory accommodates multi-format and/or reduced video data storage. The address generation engine includes a processor and address generation hardware. The processor, coupled to access encoded data to be decoded by the digital video decoder unit, has microcode for deriving from the encoded data relative location information including a vertical component and a horizontal component. The address generation hardware includes a row address register and a column address register for receiving the vertical component and horizontal component, respectively, derived by the processor. The address generation hardware is configured for generating from the vertical component and the horizontal component either a macroblock write address for writing a reconstructed macroblock of data to memory, a motion compensation read address for accessing pertinent motion vector information of the encoded data for reconstructing the macroblock, and a pan and scan offset address usable by a display unit for displaying reconstructed video data in pan and scan format.

Claims

1. An address generation engine for a digital video decoder unit coupled to memory, said address generation engine comprising:

a processor coupled to access an encoded video signal to be decoded by said digital video decoder unit, said processor having microcode for deriving from said encoded video signal relative location information including a vertical component and a horizontal component; and

address generation hardware including a row address register and a column address register for receiving the vertical component and horizontal component, respectively, of said relative location information derived by said processor, said address generation hardware being coupled to and initiated by said processor and being configured to generate from said vertical component and horizontal component at least one of a macroblock write address, a motion compensation read address, and a pan and scan offset address, wherein said at least one of said macroblock write address, said motion compensation read address and said pan and scan offset address is generated in hybrid fashion using said microcode of said processor and said address generation hardware.

2. The address generation engine of claim 1, wherein said macroblock write address is usable for writing a decoded macroblock of data from said digital video decoder unit to said memory, said motion compensation read address is usable by a motion compensation unit of said digital video decoder unit in accessing pertinent motion vector information of said encoded digital video signal when stored in said memory, and said pan and scan offset address is usable by a display unit coupled to said digital video decoder unit for displaying decoded video data in pan and scan format.

3. The address generation engine of claim 2, wherein said address generation hardware generates from said vertical component and said horizontal component said macroblock write address, and wherein said vertical component comprises a row address of a reconstructed macroblock of a current picture being decoded and said horizontal component comprises a column address of the reconstructed macroblock of the current picture.

4. The address generation engine of claim 3, wherein said row address is defined as (SLICE-1) HSIZE and said column address is defined as a macroblock column in macroblock units.

5. The address generation engine of claim 2, wherein said address generation hardware generates from said vertical component and said horizontal component said motion compensation read address, and wherein said vertical component and horizontal component comprise addresses derived from motion vector information.

6. The address generation engine of claim 5, wherein said vertical component for generating said motion compensation read address comprises VERT_-- COMP·

HSIZE in 2'"'"'s complement, and said horizontal component comprises HOR_-- COMP in 2'"'"'s complement in pixel units.

7. The address generation engine of claim 2, wherein said address generation hardware generates from said vertical component and said horizontal component said pan and scan offset address, and wherein said vertical component and said horizontal component comprise row and column address information, respectively, derived from pan and scan vectors in the encoded video signal to be decoded.

8. The address generation engine of claim 2, wherein said vertical component comprises VERT_-- OFFSET·

HSIZE, and said horizontal component comprises HOR_-- OFFSET in pixel units.

9. The address generation engine of claim 1, wherein said address generation hardware comprises means for generating under control of said processor each of said macroblock write address, said motion compensation read address, and said pan and scan offset address with receipt at said address generation hardware of corresponding vertical components and horizontal components.

10. The address generation engine of claim 1, wherein said memory accommodates one or more of content scaled data, reduction scaled data and letterbox mode data and wherein said address generation hardware comprises means for at least one of content scaling, reduction scaling and letterbox mode scaling said vertical component and said horizontal component of said relative location information derived by said processor in generating either said macroblock write address or said pan and scan offset address.

11. The address generation engine of claim 1, wherein said address generation hardware further comprises an HSIZE register coupled in parallel with said row address register and said column address register, and wherein output of said HSIZE register, said row address register and said column address register is each coupled through a respective shifter to a different input of a multi-input adder, wherein an output of said adder comprises said at least one of the macroblock write address, the motion compensation read address, and the pan and scan offset address.

12. The address generation engine of claim 11, wherein said address generation hardware further comprises a state machine coupled to said shifters and to said multi-input adder, said state machine being controlled by said processor and controlling generation of said at least one of the macroblock write address, the motion compensation read address, and the pan and scan offset address.

13. The address generation engine of claim 12, wherein said processor provides address generation control signals to said state machine of said address generation hardware to control initiation and generation of said at least one of said macroblock write address, said motion compensation read address, and said pan and scan offset address.

14. The address generation engine of claim 13, wherein said processor and said address generation hardware comprise means for generating in said hybrid fashion the macroblock write address to memory for a macroblock to be reconstructed and then the motion compensation read address for use in reconstructing the macroblock.

15. A digital video decoder system for decoding an encoded digital video signal, said system comprising:

memory and a memory controller for temporarily storing the encoded digital video signal;

a variable length code (VLC) decoder coupled to said memory for decoding encoded data of the encoded digital video signal, thereby producing decoded data;

an inverse quantizer (IQ) coupled to the VLC decoder for dequantizing the decoded data to produce therefrom dequantized, decoded data;

a discrete cosine transform inverter (IDCT) coupled to the IQ for transforming the dequantized, decoded data from frequency domain to spatial domain, said spatial domain, dequantized decoded data including difference data;

a motion compensator (MC) and adder for receiving reference data from said memory and said difference data from the IDCT to form motion compensated pictures therefrom; and

a hybrid address engine coupled to said MC and to a display unit of said digital video decoder system for providing addressing to said memory, said hybrid address engine comprising;

a processor coupled to memory to access the encoded data to be decoded, said processor having microcode for deriving from said encoded data relative location information including a vertical component and a horizontal component; and

address generation hardware including a row address register and a column address register for receiving the vertical component and horizontal component, respectively, determined by said processor, said address generation hardware being coupled to and initiated by said processor and being configured to generate from said vertical component and horizontal component at least one of a macroblock write address, a motion compensation read address and a pan and scan offset address, wherein said at least one of said macroblock write address, said motion compensation read address and said pan and scan offset address is generated in hybrid fashion using said microcode of said processor and said address generation hardware.

16. The digital video decoder system of claim 15, wherein said memory comprises means for storing at least one of content scaled data, reduction scaled data and letterbox mode data, and wherein said address generation hardware comprises means for at least one of content scaling, reduction scaling and letterbox mode scaling said vertical component and said horizontal component of said relative location information derived by said processor in generating either said macroblock write address or said pan and scan offset address.

17. The digital video decoder system of claim 15, wherein said macroblock write address is usable for writing a decoded macroblock of data from said digital video decoder unit to said memory, said motion compensation read address is usable by said motion compensation unit in accessing pertinent motion vector information of said encoded data, and said pan and scan offset address is usable by said display unit of said digital video decoder system for displaying decoded video data in pan and scan format.

18. The digital video decoder system of claim 17, wherein said address generation hardware is usable to generate under control of said processor each of said macroblock write address, said motion compensation read address, and said pan and scan offset address.

19. The digital video decoder system of claim 18, wherein said address generation hardware includes a state machine and wherein said processor is coupled to and provides control signals to said state machine to control selection and generation of said at least one of said macroblock write address, said motion compensation read address, and said pan and scan offset address by said address generation hardware.

20. The digital video decoder system of claim 19, wherein said address generation hardware further comprises an HSIZE register coupled in parallel with said row address register and said column address register, and wherein output of said HSIZE register, said row address register and said column address register is each coupled through a respective shifter to a different input of a multi-input adder, wherein an output of said adder comprises said at least one of the macroblock write address, the motion compensation read address, and the pan and scan offset address, and wherein said state machine is coupled to said shifters and to said multi-input adder to control generation of said at least one of the macroblock write address, the motion compensation read address, and the pan and scan offset address.

21. The digital video decoder system of claim 20, wherein said shifter at the output of said HSIZE register is coupled to said multi-input adder across a 2-input MUX, and one input of said 2-input MUX comprises an output of said multi-input adder, and wherein said state machine is also coupled to said MUX for selecting between said two inputs.

22. The digital video decoder system of claim 15, wherein said macroblock write address, said motion compensation read address and said pan and scan offset address each comprise corresponding luminance and chrominance addresses to said memory.

23. In a digital video decoder system for decoding an encoded video signal, a hybrid address generation method for use within a digital video decoder unit for addressing memory of the digital video decoder system, said method comprising:

using microcode of a processor, coupled to access encoded data to be decoded by the digital video decoder unit, to generate therefrom relative location information including a vertical component and a horizontal component; and

using address generation hardware coupled to the processor to generate from said vertical component and said horizontal component at least one of a macroblock write address, a motion compensation read address, and a pan and scan offset address, wherein said at least one of said macroblock write address, said motion compensation read address and said pan and scan offset address is generated in hybrid fashion using said microcode of said processor and said address generation hardware.

24. The hybrid address generation method of claim 23, wherein said using address generation hardware comprises initiating and operating said address generation hardware pursuant to address generation control signals received from said processor.

25. The hybrid address generation method of claim 24, wherein the macroblock write address is usable for writing a decoded macroblock of data from the digital video decoder unit to memory, the motion compensation read address is usable by a motion compensation unit of the digital video decoder unit in accessing pertinent motion vector information of the encoded data when stored in memory, and the pan and scan offset address is usable by a display unit coupled to the digital video decoder unit for displaying decoded video data in pan and scan format.

26. The hybrid address generation method of claim 23, wherein said memory comprises means for storing at least one of content scaled data, reduction scaled data and letterbox mode configured data, and wherein said using address generation hardware comprises using said address generation hardware for generating under control of said processor either the macroblock write address or pan and scan offset address for storage of decoded video data in memory as at least one of content scaled data, reduction scaled data and letterbox mode configured data.

27. The hybrid address generation method of claim 26, further comprising using said microcode of said processor and said address generation hardware to generate said macroblock write address for a macroblock to be reconstructed and then to generate said motion compensation read address for accessing pertinent motion vector information in the encoded data for use in reconstructing the macroblock.

28. The hybrid address generation method of claim 27, wherein said using microcode of the processor comprises employing said microcode to continue to parse the encoded data for motion vectors after initiating the address generation hardware to generate said macroblock write address, and wherein said using microcode further comprises using microcode of the processor to check for completion by said address generation hardware of said generating of the macroblock write address, and upon detecting said completion, for initiating said address generation hardware to generate said motion compensation read address for the motion vectors processed from the encoded data.