Clock-synchronous type semiconductor memory device capable of outputting read clock signal at correct timing

• US 5,963,502 A
• Filed: 07/09/1998
• Issued: 10/05/1999
• Est. Priority Date: 01/14/1998
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Watanabe, Naoya, Yoshimura, Tsutomu, Morooka, Yoshikazu, Nakase, Yasunobu
• Primary Examiner(s): LE, VU ANH
• Application Number:
  US09/112,439
• Time in Patent Office: 453 Days
• Field of Search: 365/233, 365/194, 327/161, 327/141, 327/146, 327/147, 327/153, 327/156
• US Class Current: 365/233.1
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management

Abstract

A voltage controlled delay circuit having the same structure, except for a loop, as a voltage controlled oscillator included in a PLL circuit which in turn generates an internal clock signal from an external clock signal is controlled by a control voltage from the PLL circuit, and the delay output of the voltage controlled delay circuit is selected by a selection circuit in accordance with the output signal of a vernier-adjusting counter in order to generate a read clock signal. Therefore, a vernier for optimizing data input timing in a controller can be realized which always has a constant delay amount regardless of a change in operating environment.

Claims

1. A synchronous type semiconductor memory device, comprising:

a phase synchronization circuit for generating an internal clock signal synchronized in phase with an externally supplied external clock signal, said phase synchronization circuit including a voltage controlled oscillator having a feedback loop from an output portion thereof to an input portion thereof and having an oscillating frequency controlled by a control voltage corresponding to a phase difference between said external clock signal and said internal clock signal;

a read clock generator for generating a read clock signal from said internal clock signal for external outputting when data is read, said read clock generator including a variable delay circuit having a same structure as said voltage controlled oscillator except for said feedback loop and receiving a signal corresponding to said internal clock signal at an input portion thereof; and

a vernier setting circuit for setting a delay amount of said variable delay circuit in accordance with an external command.

2. The synchronous type semiconductor memory device according to claim 1, wherein

said voltage controlled oscillator includes a plurality of cascaded delay circuits each having an operating current controlled by said control voltage, and an input at a first stage and an output at a last stage of said plurality of delay circuits are connected by said feedback loop, and

said variable delay circuit includes

a plurality of cascaded second delay circuits of a same number as the plurality of delay circuits of said voltage controlled oscillator, each second delay circuit having an operating current controlled by said control voltage, and

a selection circuit selecting an output signal of said plurality of second delay circuits in accordance with an output signal of said vernier setting circuit for outputting as said read clock signal.

3. The synchronous type semiconductor memory device according to claim 1, wherein

a unit delay amount of said variable delay circuit is set at 1/m times one cycle period of said external clock signal, in which m is an odd number of at least 3.

4. The synchronous type semiconductor memory device according to claim 2, wherein

each second delay circuit of said variable delay circuit is formed of inverters, and said selection circuit selects one of an input clock signal at the input portion thereof and outputs of inverters at even stages in accordance with the output signal of said vernier setting circuit.

5. The synchronous type semiconductor memory device according to claim 2, wherein

said vernier setting circuit includes a multi-bit up/down counter having its count value of multi-bits increased and decreased, and

said selection circuit includes a gate circuit provided corresponding to each bit of said multi-bit up/down counter for selecting an output of the second delay circuits in response to the multi-bits.

6. The synchronous type semiconductor memory device according to claim 5, wherein

said multi-bit up/down counter has each bit corresponding to an integer times said unit delay amount and functions as a shift circuit having a bit out of the multi-bits to be activated at a time, and

said gate circuit includes a transfer gate arranged between each output portion of the second delay circuit corresponding to an integer multiple of said unit delay amount and an output node outputting the read clock signal and corresponding to each bit of said multi-bit up/down counter and rendered conductive when a corresponding bit of the multi-bits is activated for connecting the output portion of a corresponding second delay circuit to said output node.

7. The synchronous type semiconductor memory device according to claim 3, wherein

said variable delay circuit includes delay circuits each formed of inverters, and

said selection circuit selects one of an input clock signal at the input portion thereof and outputs of inverters at even stages in accordance with an output signal of said vernier setting circuit.

8. The synchronous type semiconductor memory device according to claim 1, wherein said read clock generator receives a clock signal generated from said internal clock signal when data is read.

9. The synchronous type semiconductor memory device according to claim 1, further comprising

data offset vernier circuitry including a variable delay circuit having a same structure as the voltage controlled oscillator except for the feedback loop, for generating a data output clock signal from the read clock signal, and

data output circuitry for externally outputting read data in synchronization with said data output clock signal.