Synchronous systems having secondary caches

• US 5,963,503 A
• Filed: 11/09/1998
• Issued: 10/05/1999
• Est. Priority Date: 11/15/1997
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd. (Samsung Group)
• Original Assignee: Samsung Electronics Co. Ltd. (Samsung Group)
• Inventors: Lee, Young-Dae
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Nguyen, Tuan T.
• Application Number:
  US09/188,075
• Time in Patent Office: 330 Days
• Field of Search: 365/233, 365/230.03, 365/230.06
• US Class Current: 365/233.1
• CPC Class Codes: G11C 11/408 Address circuits
• CPC Class Codes: G11C 11/4087 Address decoders, e.g. bit - or word line decoders; Multiple line decoders
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories

Abstract

A cache memory uses at least two synchronous memory devices operable of responding to an external clock signal and performing a bank operation mode. The memory device includes a control logic for generating an informing signal denoting a non-selection of the memory device, the informing signal responding to the internal clock signal, a first decoder generating a first selection signal to designate one of the second word lines and a second selection signal to designate one of the first word lines corresponding to the first word line which is preliminarily selected, a control signal generating circuit receiving the informing signal and generating a control signal responding to the internal clock signal, and a second decoder for receiving the first and second selection signals and for selecting the first word line, when the memory device is being selected. When the memory device goes to a selection state from a non-selection state, the control signal is enabled until the first and second selection signals are applied to the second decoder, during a cycle time of the informing signal.

Claims

1. A synchronous memory device operable of responding to an external clock signal comprising:

a memory cell array having a plurality of memory cells arranged in a matrix formed of rows and columns;

a plurality of first and second word lines, a connection ratio of the first and second word lines being 1;

n (n is at least greater than

     1);

a clock generator for generating an internal clock signal responding to the external clock signal;

a control logic for generating an informing signal denoting a non-selection of the memory device, the informing signal responding to the internal clock signal;

a first decoder for receiving row address signals to designate one of the first word lines, and for generating a first selection signal to designate one of the second word lines and a second selection signal to designate one of the first word lines corresponding to the first word line preliminarily selected;

a control signal generating circuit for receiving the informing signal and for generating a control signal responding to the internal clock signal; and

a second decoder for receiving the first and second selection signals and for selecting the first word line, when the memory device is being selected;

whereby, when the memory device goes to a selection state from a non-selection state, the control signal is enabled until the first and second selection signals are applied to the second decoder, during a cycle time of the informing signal.

2. A system having a processing unit and a cache memory at least formed of two synchronous memory devices, the synchronous memory device comprising:

a memory cell array having a plurality of memory cells arranged in a matrix formed of rows and columns;

a plurality of first and second word lines, a connection ratio of the first and second word lines being 1;

n (n is at least greater than

     1);

a clock generator for generating an internal clock signal responding to the external clock signal;

a control logic for generating an informing signal denoting a non-selection of the memory device, the informing signal responding to the internal clock signal;

a first decoder for receiving row address signals to designate one of the first word lines, and for generating a first selection signal to designate one of the second word lines and a second selection signal to designate one of the first word lines corresponding to the first word line which preliminarly selected;

a control signal generating circuit for receiving the informing signal and for generating a control signal responding to the internal clock signal; and

a second decoder for receiving the first and second selection signals and for selecting the first word line, when the memory device is being selected;

whereby, when the memory device goes to a selection state from a non-selection state, the control signal is enabled until the first and second selection signals are applied to the second decoder, during a cycle time of the informing signal.