Address transition detection in a synchronous design

• US 5,963,504 A
• Filed: 12/19/1997
• Issued: 10/05/1999
• Est. Priority Date: 12/23/1994
• Status: Expired due to Term

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Manning, Troy A.
• Primary Examiner(s): YOO, DO H
• Application Number:
  US08/994,180
• Time in Patent Office: 655 Days
• Field of Search: 365/233.5, 365/230.08, 365/189.05, 365/202, 365/230.02, 365/189.02, 365/193
• US Class Current: 365/233.5
• CPC Class Codes: G06F 12/0638 Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module address formation of the next microinstruction G06F9/26; masking faults in memories by using spares or by reconfiguring G11C29/70
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G11C 11/407 for memory cells of the field-effect type
• CPC Class Codes: G11C 7/1018 Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
• CPC Class Codes: G11C 7/1021 Page serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled column address stroke pulses each with its associated bit line address
• CPC Class Codes: G11C 7/1024 Extended data output [EDO] mode, i.e. keeping output buffer enabled during an extended period of time
• CPC Class Codes: G11C 7/1039 using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/109 Control signal input circuits
• CPC Class Codes: G11C 7/1096 Write circuits, e.g. I/O line write drivers

Abstract

An integrated circuit memory device is designed to perform high speed burst access read and write cycles. An address strobe signal is used to latch a first address. During a burst access cycle the address is incremented internal to the device with additional address strobe transitions. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating the need to toggle the Read/Write control line at the device cycle frequency. A transition of the Read/Write control line during a burst access is used to terminate the burst access and initialize the device for another burst access. The memory device maintains compatibility with nonburst mode devices such as Extended Data Out (EDO) and Fast Page Mode through bond option or mode selection circuitry. A multiplexer selects between the input address and the burst address generator output to feed an asynchronous address transition detection circuit. The address transition detection circuit generates an equilibration control signal between memory access cycles.

Claims

1. A method of operating address circuitry in a memory device, the method comprising:

receiving a first address from a source external to the memory device;

latching the first address;

generating a next address using an address generation circuit, the next address being generated based upon the first address;

providing a multiplexed signal by multiplexing either the first address or the next address to an address transition detection circuit for detecting a difference between a current address and a prior address;

latching the multiplexed signal; and

generating an equilibration signal if a difference is detected between the current address and the prior address.

2. The method of claim 1 wherein latching the multiplexed signal is performed by coupling an output of a multiplex circuit to an input of the multiplex circuit.

3. The method of claim 1 wherein the memory device is a synchronous dynamic random access memory (SDRAM).

4. The method of claim 1 wherein the next address is generated while the memory device is in a burst mode.

5. The method of claim 1 wherein the equilibration signal equilibrates input/output data communication lines.