Error detection and correction apparatus for an asynchronous transfer mode (ATM) network device

• US 5,963,543 A
• Filed: 08/05/1997
• Issued: 10/05/1999
• Est. Priority Date: 10/20/1993
• Status: Expired due to Term

• Current Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Rostoker, Michael D., Stelliga, D. Tony
• Primary Examiner(s): MARCELO, MELVIN C
• Application Number:
  US08/906,566
• Time in Patent Office: 791 Days
• Field of Search: 370/229-237, 370/395
• US Class Current: 370/232
• CPC Class Codes: G06F 13/128 for dedicated transfers to a network for protocol converters G06F13/387
• CPC Class Codes: H04L 12/5602 Bandwidth control in ATM Networks, e.g. leaky bucket
• CPC Class Codes: H04L 2012/5613 Bus (including DQDB)
• CPC Class Codes: H04L 2012/5614 User Network Interface
• CPC Class Codes: H04L 2012/5615 Network termination, e.g. NT1, NT2, PBX
• CPC Class Codes: H04L 2012/5616 Terminal equipment, e.g. codecs, synch.
• CPC Class Codes: H04L 2012/5628 Testing
• CPC Class Codes: H04L 2012/5632 Bandwidth allocation
• CPC Class Codes: H04L 2012/5635 Backpressure, e.g. for ABR
• CPC Class Codes: H04L 2012/5636 Monitoring or policing, e.g. compliance with allocated rate, corrective actions
• CPC Class Codes: H04L 2012/5637 Leaky Buckets
• CPC Class Codes: H04L 2012/5638 Services, e.g. multimedia, GOS, QOS
• CPC Class Codes: H04L 2012/5647 Cell loss
• CPC Class Codes: H04L 2012/5652 Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly
• CPC Class Codes: H04L 2012/5653 using the ATM adaptation layer [AAL]
• CPC Class Codes: H04L 2012/5664 Support of Video, e.g. MPEG
• CPC Class Codes: H04L 2012/5665 Interaction of ATM with other protocols
• CPC Class Codes: H04L 43/00 Arrangements for monitoring or testing data switching networks
• CPC Class Codes: H04L 43/0817 by checking functioning
• CPC Class Codes: H04L 43/0852 Delays
• CPC Class Codes: H04L 43/0894 : Packet rate
• CPC Class Codes: H04L 43/10 : Active monitoring, e.g. heartbeat, ping or trace-route
• CPC Class Codes: H04L 43/106 : using time related information in packets, e.g. by adding timestamps
• CPC Class Codes: H04L 45/745 : Address table lookup; Address filtering
• CPC Class Codes: H04L 47/10 : Flow control; Congestion control
• CPC Class Codes: H04L 47/11 : Identifying congestion
• CPC Class Codes: H04L 47/263 : Rate modification at the source after receiving feedback
• CPC Class Codes: H04L 47/43 : Assembling or disassembling of packets, e.g. segmentation and reassembly [SAR]
• CPC Class Codes: H04L 49/20 : Support for services
• CPC Class Codes: H04L 49/30 : Peripheral units, e.g. input or output ports
• CPC Class Codes: H04L 49/3009 : Header conversion, routing tables or routing tags
• CPC Class Codes: H04L 49/3081 : ATM peripheral units, e.g. policing, insertion or extraction
• CPC Class Codes: H04L 49/501 : Overload detection
• CPC Class Codes: H04L 49/555 : Error detection
• CPC Class Codes: H04L 49/557 : Error correction, e.g. fault recovery or fault tolerance
• CPC Class Codes: H04L 49/90 : Buffering arrangements
• CPC Class Codes: H04L 49/901 : using storage descriptor, e.g. read or write pointers
• CPC Class Codes: H04L 49/9094 : Arrangements for simultaneous transmit and receive, e.g. simultaneous reading/writing from/to the storage element
• CPC Class Codes: H04N 19/00 : Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
• CPC Class Codes: H04N 19/42 : characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation H04N19/635 takes precedence
• CPC Class Codes: H04N 19/61 : in combination with predictive coding
• CPC Class Codes: H04N 19/70 : characterised by syntax aspects related to video coding, e.g. related to compression standards
• CPC Class Codes: H04N 21/2381 : Adapting the multiplex stream to a specific network, e.g. an Internet Protocol [IP] network transmission of MPEG streams over ATM H04L12/5601
• CPC Class Codes: H04N 21/4381 : Recovering the multiplex stream from a specific network, e.g. recovering MPEG packets from ATM cells transmission of MPEG streams over ATM H04L12/5601
• CPC Class Codes: H04N 21/6137 : involving transmission via a telephone network, e.g. POTS
• CPC Class Codes: H04N 21/64307 : ATM
• CPC Class Codes: H04N 21/6473 : Monitoring network processes errors for recovering from a failure of a protocol instance or entity H04L69/40
• CPC Class Codes: H04N 21/64738 : Monitoring network characteristics, e.g. bandwidth, congestion level data switched network analysis H04L41/14; monitoring functioning in data switched networks H04L43/0817; flow control in packet networks H04L47/10
• CPC Class Codes: H04N 21/64792 : Controlling the complexity of the content stream, e.g. by dropping packets intermediate media network packet handling H04L65/765; proxy provisioning conversion or adaptation for reducing the amount or size of exchanged application data H04L67/5651; negotiation of resources in wireless networks H04W28/16
• CPC Class Codes: H04Q 11/0478 : Provisions for broadband connections
• CPC Class Codes: H04Q 2213/13034 : A/D conversion, code compression/expansion
• CPC Class Codes: H04Q 2213/13097 : Numbering, addressing
• CPC Class Codes: H04Q 2213/13141 : Hunting for free outlet, circuit or channel
• CPC Class Codes: H04Q 2213/13174 : Data transmission, file transfer
• CPC Class Codes: H04Q 2213/13204 : Protocols
• CPC Class Codes: H04Q 2213/13216 : Code signals, frame structure
• CPC Class Codes: H04Q 2213/13296 : Packet switching, X.25, frame relay
• CPC Class Codes: H04Q 2213/13322 : Integrated circuits
• CPC Class Codes: H04Q 2213/13332 : Broadband, CATV, dynamic bandwidth allocation
• CPC Class Codes: H04Q 2213/13353 : Routing table, map memory
• CPC Class Codes: Y02D 30/50 : in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

An adaptive error detection and correction apparatus for an Asynchronous Transfer Mode (ATM) network device comprises a sensing unit for sensing a congestion condition in the ATM network and a global pacing rate unit for adaptively reducing a maximum allowable transmission ratio of ATM cells containing information to idle ATM cells in response to a sensed congestion condition. A processor stores a number corresponding to a relatively high maximum allowable transmission ratio in the global pacing rate register in the absence of a sensed congestion condition, and stores a number corresponding to a relatively low maximum allowable transmission ratio in the global pacing rate register in response to a sensed congestion condition. A controller adjusts the maximum allowable transmission ratio in accordance with the number stored in the global pacing rate register. A plurality of peak pacing rate counters reset to predetermined values upon decrementation to zero, the predetermined values corresponding to service intervals for segmentation of Conversion Sublayer Payload Data Unit (CD-PDU)s. The processor further includes circuitry for assigning the counters to selected CD-PDUs, and sensing the counters to determine whether or not segmentation of the selected CD-PDUs is within the respective service intervals. The apparatus further includes a channel group credit register having bits corresponding to the respective counters.

Claims

1. Integrated circuitry for detecting and correcting errors in an asynchronous transfer mode (ATM) network, the ATM network having a transmission ratio defined as a ratio of cells which contain information to cells which are idle, said integrated circuitry comprising on a single chip:

sensing circuitry for sensing a congestion condition in the ATM network; and

global pacing rate circuitry in communication with said sensing circuitry for reducing a maximum allowable transmission ratio in response to a congestion condition;

said sensing circuitry and said global pacing rate circuitry being disposed on a single chip.

2. Integrated circuitry as claimed in claim 1 wherein said global pacing rate circuitry comprises:

a global pacing rate register;

processing circuitry for storing a number corresponding to a relatively high maximum allowable transmission ratio in said global pacing rate register in the absence of a sensed congestion condition, and for storing a number corresponding to a relatively low maximum allowable transmission ratio in said global pacing rate register in response to a sensed congestion condition; and

controlling circuitry for adjusting said maximum allowable transmission ratio in accordance with said number stored in said global pacing rate register.

3. Programmable pacing rate circuitry for an asynchronous transfer mode (ATM) network device, the ATM network having a transmission ratio defined as a ratio of cells which contain information to cells which are idle, said pacing rate circuitry comprising on a single chip:

sensing circuitry for sensing a congestion condition in the ATM network; and

global pacing rate circuitry for reducing a maximum allowable transmission ratio in response to a sensed congestion condition;

said sensing circuitry and said global pacing rate circuitry being disposed on a single chip.

4. Circuitry as claimed in claim 3 wherein said global pacing rate circuitry comprises:

a global pacing rate register;

processing circuitry for storing a number corresponding to a relatively high maximum allowable transmission ratio in said global pacing rate register in the absence of a sensed congestion condition, and storing a number corresponding to a relatively low maximum allowable transmission ratio in said global pacing rate register in response to a sensed congestion condition; and

controlling circuitry for adjusting said maximum allowable transmission ratio in accordance with said number stored in said global pacing rate register.

5. Circuitry as claimed in claim 3 further comprising on said single chip a plurality of peak pacing rate counters which reset to predetermined values upon decrementing to zero, said predetermined values corresponding to service intervals for segmentation of conversion sublayer payload data units (CD-PDUs);

wherein said processing circuitry comprises circuitry for assigning said counters to selected CD-PDUs and sensing said counters to determine whether or not segmentation of said selected CD-PDUs is within said service interval respectively.

6. Circuitry as claimed in claim 5 wherein said processing circuitry further comprises circuitry for designating a plurality of CD-PDUs having similar characteristics and causing said plurality of CD-PDUs to be segmented simultaneously as a channel group.

7. Circuitry as claimed in claim 6 further comprising on said single chip a channel group credit register having bits respectively corresponding to the counters, said bits being set to a first logical sense prior to segmentation of a channel group and being set to a second logical sense upon decrementing of the respective counter;

wherein said processing circuitry comprises circuitry for designating a channel group as being credited for transmission if the respective bit in the channel group credit register has said second logical sense.

8. Circuitry as claimed in claim 6 wherein said processing circuitry further comprises circuitry for assigning priorities to channel groups and causing channel groups to be segmented in order of priority.

9. Circuitry as claimed in claim 5 wherein said processing circuitry further comprises circuitry for selectively stalling the counters.

10. Circuitry as claimed in claim 5 wherein said processing circuitry further comprises circuitry for combining two of the counters in series for operation as a single counter.