Method and apparatus for parallel noncoherent correlation of a spread spectrum signal

• US 5,963,586 A
• Filed: 06/07/1995
• Issued: 10/05/1999
• Est. Priority Date: 09/09/1994
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Omnipoint Corp. (Deutsche Telekom AG)
• Inventors: Durrant, Randolph L., Burbach, Mark
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): GLUCK, JEFFREY WILLIAM
• Application Number:
  US08/486,824
• Time in Patent Office: 1,581 Days
• Field of Search: 375/200, 375/206, 375/208, 375/209, 375/210, 375/274, 375/336, 375/343
• US Class Current: 375/142
• CPC Class Codes: H04B 1/707 using direct sequence modulation
• CPC Class Codes: H04B 1/708 Parallel implementation
• CPC Class Codes: H04B 1/7093 Matched filter type
• CPC Class Codes: H04B 2201/70701 featuring pilot assisted reception
• CPC Class Codes: H04J 13/10 Code generation
• CPC Class Codes: H04J 14/005 Optical Code Multiplex
• CPC Class Codes: H04L 27/2014 in which the phase changes in a piecewise linear manner during each symbol period, e.g. minimum shift keying, fast frequency shift keying H04L27/201 takes precedence
• CPC Class Codes: H04L 27/2278 using correlation techniques, e.g. for spread spectrum signals
• CPC Class Codes: H04L 27/2332 using a non-coherent carrier

Abstract

A technique for modulating and demodulating CPM spread spectrum signals and variations of CPM spread spectrum signals. A transmitter divides a signal data stream into a plurality of data streams (such as I and Q data streams), independently modulates the I and Q data streams using CPM or a related technique, and superposes the plurality of resultants for transmission. A receiver receives the superposed spread spectrum signal and simultaneously attempts to correlate for a plurality of chip sequences (such as I and Q chip sequences), and interleaves the correlated I and Q data streams into a unified signal data stream. In one embodiment, the receiver separates the received spread spectrum signal into real and imaginary parts, attempts to correlate both real and imaginary parts for a plurality of chip sequences, and combines the real I, real Q, imaginary I, and imaginary Q signals into a unified signal data stream. The demodulating reference signal in the receiver may or may not be frequency or phase matched with the transmitter. In other embodiments, single bit or multi-bit digitization of the received spread spectrum signal for both I and Q signals (or real I, real Q, imaginary I, and imaginary Q signals) is carried out prior to correlation. In another embodiment, the transmitter differentially phase encodes the information to be transmitted, and the receiver decodes the phase encoded information by determining a quantized phase angle of the received signal.

Claims

1. A method for despreading a received continuous phase modulated spread spectrum signal comprising the steps of:

dividing a received spread spectrum signal into a first signal and a second signal, said first and second signal being duplicates of one another,

demodulating said first signal into a real-I/imaginary-Q signal using a first non-coherent local reference signal,

demodulating said second signal into an imaginary-I/real-Q signal using a second non-coherent local reference signal having the same frequency as said first non-coherent local reference signal but phase offset therefrom by 90 degrees,

temporarily storing said real-I/imaginary-Q signal in a single first register,

temporarily storing said imaginary-I/real-Q signal in a single second register,

correlating the contents of said first register to generate a real I correlation signal and an imaginary Q correlation signal, said contents of said first register comprising odd and even chips, said odd chips being correlated with odd chips of a chip sequence and said even chips being correlated with inverses of even chips of said chip sequence,

correlating the contents of said second register to generate an imaginary I correlation signal and a real Q correlation signal, said contents of said second register comprising odd and even chips, said odd chips being correlated with odd chips of said chip sequence and said even chips being correlated with said even chips of said chip sequence, and

combining said real I correlation signal, said real Q correlation signal, said imaginary I correlation signal and said imaginary Q correlation signal into a final correlation signal.

2. The method of claim 1 wherein each of said first register and said second register comprises a series of chip locations, and wherein said step of correlating the contents of said first register and said step of correlating the contents of said second register each further comprises the steps of

comparing alternating ones of said chip locations with the odd chips of a chip sequence to generate a plurality of I comparison signals,

combining said I comparison signals into an I correlation signal,

comparing alternating ones of said chip locations either with the even chips of said chip sequence for said second register or with the inverse of said even chips for said first register to generate a plurality of Q comparison signals, and

combining said Q comparison signals into a Q correlation signal.

3. The method of claim 1 wherein said step of combining further comprises the steps of:

summing said real I correlation signal and said real Q correlation signal to generate a real correlation signal,

summing said imaginary I correlation signal and said imaginary Q correlation signal to generate an imaginary correlation signal, and

computing a square root of a sum of a square of said real correlation signal and a square of said imaginary correlation signal to generate said final correlation signal.

4. A method for despreading a received continuous phase modulated spread spectrum signal comprising the steps of:

dividing a received spread spectrum signal into a first signal and a second signal, said first and second signal being duplicates of one another,

demodulating said first signal into a first demodulated signal using a first non-coherent local reference signal,

demodulating said second signal into a second demodulated signal using a second non-coherent local reference signal having the same frequency as said first non-coherent local reference signal but phase offset therefrom by 90 degrees,

temporarily storing said first demodulated signal in a single first register,

temporarily storing said second demodulated signal in a single second register,

correlating the contents of said first register, said contents comprising a plurality of chips, to generate a first correlation signal based on a correlation of odd chips of said first register with a plurality of odd chips of a chip sequence, and a second correlation signal based on a correlation of even chips of said first register with inverses of a plurality of even chips of said chip sequence,

correlating the contents of said second register, said contents comprising a plurality of chips, to generate a third correlation signal based on a correlation of odd chips of said second register with said odd chips of said chip sequence, and a fourth correlation signal based on a correlation of even chips of said second register with said even chips of said chip sequence, and

combining said first correlation signal, said second correlation signal, said third correlation signal and said fourth correlation signal into a final correlation signal.

5. The method of claim 4 wherein each of said first register and said second register comprises a series of chip locations, and wherein said step of correlating the contents of said first register and said step of correlating the contents of said second register each further comprises the steps of:

comparing alternating ones of said chip locations with the odd chips of a chip sequence to generate a first plurality of comparison signals,

combining each of said first plurality of comparison signals into a first combined correlation signal,

comparing alternating ones of said chip locations either with the even chips of said chip sequence for said second register or with the inverse of said even chips for said first register to generate a second plurality of comparison signals, and

combining each of said second plurality of comparison signals into a second combined correlation signal.

6. The method of claim 4 wherein said step of combining further comprises the steps of:

summing said first correlation signal and said fourth correlation signal to generate a fifth correlation signal,

summing said second correlation signal and said third correlation signal to generate a sixth correlation signal, and

computing a square root of a sum of a square of said fifth correlation signal and a square of said sixth correlation signal.

7. An apparatus for despreading a received continuous phase modulated spread spectrum signal comprising:

a power divider having as an input a received spread spectrum signal and having as outputs a first signal and a second signal,

a first multiplier coupled to said first signal and a first local reference signal and having as an output a third signal, said first local reference signal differing in phase and small amounts of frequency from a carrier in said spread spectrum signal,

a second multiplier coupled to said second signal and a second local reference signal and having as an output a fourth signal, said second local reference signal phase offset from said first local reference signal by 90 degrees,

a first low pass filter coupled to said third signal and having as an output a first filtered signal,

a second low pass filter coupled to said fourth signal and having as an output a second filtered signal,

a first even/odd correlator receiving said first filtered signal and having as outputs a first correlation signal and a second correlation signal,

a second even/odd correlator receiving said second filtered signal and having as outputs a third correlation signal and a fourth correlation signal, and

means for combining said first correlation signal, said second correlation signal, said third correlation signal, and said fourth correlation signal into a final correlation signal,

said first even/odd correlator comprising

a single register having a first plurality of odd chip locations and a first plurality of even chip locations for receiving chips of said first filtered signal,

a plurality of odd chip multipliers, said odd chip locations of said first plurality of odd chip locations coupled to odd chip inputs of said plurality of odd chip multipliers for multiplication by odd chips of a chip sequence, said odd chip multipliers having first odd outputs;

a first summer having as first summer inputs said first odd outputs, and said first summer having as an output a first correlation signal,

a plurality of even chip multipliers, said even chip locations of said first plurality of even chip locations coupled to even chip inputs of said plurality of even chip multipliers for multiplication by inverses of even chips of said chip sequence, said even chip multipliers having first even chip outputs; and

a second summer having as second summer inputs said even chip outputs, and said second summer having as an output a second correlation signal;

said second even/odd correlator comprising

a single register having a second plurality of odd chip locations and a second plurality of odd chip locations and a second plurality of even chip locations for receiving chips of said third filtered signal,

a second plurality of odd chip multipliers, said odd chip locations of said second plurality of odd chip locations coupled to odd chip inputs of said second plurality of odd chip multipliers for multiplication by said odd chips of said chip sequence, said odd chip multipliers having second odd chip outputs;

a third summer having as third summer inputs said second odd chip outputs, and said third summer having a third correlation signal as an output,

a second plurality of even chip multipliers, said even chip locations of said second plurality of even chip locations coupled to even chip inputs of said second plurality of even chip multipliers for multiplication by said even chips of said chip sequence, said even chip multipliers having second even chip outputs; and

a fourth summer having as fourth summer inputs said second even chip outputs, and said fourth summer having a fourth correlation signal as an output.

8. The apparatus of claim 7 wherein said means for combining comprises:

a first summer having as inputs said first correlation signal and said fourth correlation signal,

a second summer having as inputs said second correlation signal and said third correlation signal, and

means for generating a square root of a sum of a square of an output of said first summer and a square of an output of said second summer.

9. The apparatus of claim 8 wherein said means for generating a square root of a sum of a square of an output of said first summer and a square of an output of said second summer further comprises a Robertson device.

10. An apparatus for despreading a received continuous phase modulated spread spectrum signal comprising:

a power divider having as an input a received spread spectrum signal and having as outputs a first signal and a second signal, said first signal and said second signal being duplicates of one another,

means for demodulating said first signal into a real-I/imaginary-Q signal, said means comprising a first non-coherent local reference signal,

means for demodulating said second signal into an imaginary-I/real-Q signal, said means comprising a second non-coherent local reference signal having the same frequency as said first non-coherent local reference signal but phase offset therefrom by 90 degrees,

a first even/odd correlator for correlating said real-I/imaginary-Q signal and generating a real I correlation signal and an imaginary Q correlation signal,

a second even/odd correlator for correlating said imaginary-I/real-Q signal and generating an imaginary I correlation signal and a real Q correlation signal,

means for combining said real I correlation signal, said real Q correlation signal, said imaginary I correlation signal, and said imaginary Q correlation signal into a final correlation signal,

said first even/odd correlator comprising

a single register having a first plurality of odd chip locations and a first plurality of even chip locations for receiving chips of said real I/imaginary Q signals,

a plurality of I multipliers, said odd chip locations of said first plurality of odd chip locations coupled to I inputs of said plurality of I multipliers for multiplication by odd chips of a chip sequence, said I multipliers having first I outputs;

a first I summer having as first I summer inputs said first I outputs, and said first I summer having a real I correlation signal as an output,

a plurality of Q multipliers, said even chip locations of said first plurality of even chip locations coupled to Q inputs of said plurality of Q multipliers for multiplication by inverses of even chips of said chip sequence, said Q multipliers having first Q outputs; and

a first Q summer having as first Q summer inputs said first Q outputs, and said first Q summer having an imaginary Q correlation signal as an output;

said second even/odd correlator comprising

a single register having a second plurality of odd chip locations and a second plurality of odd chip locations and a second plurality of even chip locations for receiving chips of said imaginary I/real Q signals,

a second plurality of I multipliers, said odd chip locations of said second plurality of odd chip locations coupled to I inputs of said second plurality of I multipliers for multiplication by said odd chips of said chip sequence, said I multipliers having second I outputs;

a second I summer having as second I summer inputs said second I outputs, and said second I summer having an imaginary I correlation signal as an output,

a second plurality of Q multipliers, said even chip locations of said second plurality of even chip locations coupled to Q inputs of said second plurality of Q multipliers for multiplication by said even chips of said chip sequence, said Q multipliers having second Q outputs; and

a second Q summer having as second Q summer inputs said second Q outputs, and said second Q summer having a real Q correlation signal as an output.

11. The apparatus of claim 10 wherein said means for combining comprises:

a real summer for combining said real I correlation signal and said real Q correlation signal to generate a real correlation signal,

an imaginary summer for combining said imaginary I correlation signal and said imaginary Q correlation signal to generate an imaginary correlation signal, and

means for generating a square root of a sum of a square of said real correlation signal and a square of said imaginary correlation signal.

12. A method comprising the steps of:

generating a CPM signal having a carrier frequency w₀,

transmitting said CPM signal,

receiving said CPM signal,

splitting said received CPM signal into a first received CPM signal and a second received CPM signal,

generating a local cosine waveform and a local sine waveform in said receiver, each of said waveforms having substantially the same frequency, w₁, said w₁ frequency offset from said transmitter carrier signal frequency w₀ by a variable phase shift Θ

,

modulating said first received CPM signal by said local cosine waveform to obtain a first product signal,

modulating said second received CPM signal by said local sine waveform to yield a second product signal,

low pass filtering said first product signal to provide a first filtered signal,

low pass filtering said second product signal to provide a second filtered signal,

inputting said first filtered signal into a first even/odd correlator, said first even/odd correlator comprising a single register for receiving said first filtered signal, said register thereby containing a plurality of even and odd chips of said first filtered signal,

inputting said second filtered signal into a second even/odd correlator, said second even/odd correlator comprising a single register for receiving said second filtered signal, said register thereby containing a plurality of even and odd chips of said second filtered signal,

correlating said first filtered signal in said first even/odd correlator to generate a Real I correlation signal and an Imaginary Q correlation signal, said odd chips of said first filtered signal being correlated with odd chips of a chip sequence and said even chips of said first filtered signal being correlated with inverses of even chips of said chip sequence,

correlating said second filtered signal in said second even/odd correlator to generate an Imaginary I correlation signal and a Real Q correlation signal, said odd chips of said second filtered signal being correlated with said odd chips of said chip sequence and said even chips of said second filtered signal being correlated with said even chips of said chip sequence,

summing said Real I correlation signal and said Real Q correlation signal to obtain a Real correlation signal,

summing said Imaginary I correlation signal and said Imaginary Q correlation signal to obtain an Imaginary correlation signal,

squaring each of said Real correlation and Imaginary correlation signals,

summing said squared Real and Imaginary correlation signals to obtain a unified correlation signal, and

computing a square root of said unified correlation signal.

13. The method of claim 12 wherein said step of generating a CPM signal further comprises the steps of:

dividing a chip stream into an even chip stream and an odd chip stream, and providing said even chip stream to an even channel said odd chip stream to an odd channel,

generating in said even channel a first waveform corresponding to said even chip stream,

generating in said odd channel a second waveform corresponding to said odd chip stream,

modulating said first waveform by a first carrier having a frequency w_o to generate a first modulated waveform,

modulating said second waveform by a second carrier having a frequency w_o to generate a second modulated waveform,

combining said first and second modulated waveforms to form a CPM signal.

14. The method of claim 13 wherein said chip stream is generated by translating sequences of data bits into data symbols which are used to select from a plurality of symbol codes stored in memory in said transmitter.