Method for automated electromigration verification

• US 5,963,729 A
• Filed: 06/26/1997
• Issued: 10/05/1999
• Est. Priority Date: 06/26/1997
• Status: Expired due to Term

• Current Assignee: Oracle America, Inc. (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Konstadinidis, Georgios, Aji, Sandeep A., Doreswamy, Manjunath
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): Kik, Phallaka
• Application Number:
  US08/882,986
• Time in Patent Office: 831 Days
• Field of Search: 364/488-491, 364/578, 257/767, 438/468, 438/927, 395/500.02-500.19
• US Class Current: 716/112
• CPC Class Codes: G06F 30/367 Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
• CPC Class Codes: Y10S 438/927 Electromigration resistant metallization

Abstract

An automated method detects electromigration violations in an integrated circuit design. Starting from the lowest hierarchy of the design so far completed, the parasitic (resistance and capacitance) component values extracted from a layout file are propagated up. Then, at the top-most level, lumping algorithms are employed to calculate the parasitic values for all of the top-most level nets. These values are then passed back down to the lower levels and then at each level, the layout is checked using previously computed parasitic values and EM limits. A peak current, AC-average current and AC-rms current are calculated for every layout, and then compared with the process EM rules for violations, in which the optimum line width and number of vias are specified for each interconnection.

Claims

1. A computer-implemented method for detecting electromigration violations in an integrated circuit design, the integrated circuit design having a functional hierarchy including a plurality of top-most level functional blocks each containing a plurality of functional cells, a plurality of external networks each interconnecting two or more of the top-most level functional blocks and together with the interconnected top-most level functional blocks forming a plurality of top-level nets, and further including a plurality of internal networks each contained within a respective one of the top-most level functional blocks and each interconnecting two or more functional cells within the respective one top-most level functional block, each of the external and internal networks including conductive signal traces and each of the functional cells having a drive strength associated therewith, said method comprising:

providing electromigration process rules for conductive signal traces of the integrated circuit design;

obtaining parasitic resistance and parasitic capacitance values for each conductive signal trace of the integrated circuit design;

propagating upward within the functional hierarchy the parasitic resistance and capacitance values of the conductive signal traces of the integrated circuit design;

determining a lumped resistance, a lumped capacitance and a lumped drive strength of each of the top-most level functional blocks;

determining a lumped resistance and lumped capacitance for each external network;

calculating at least one current value for each top-level net from the lumped resistance, the lumped capacitance and the lumped drive strength of the external networks and the top-most level functional blocks interconnected thereby;

determining minimum electromigration dimensions for the conductive signal traces of the integrated circuit design based on the at least one current value and said electromigration process rules for each of the top-level nets;

determining design dimensions of the conductive signal traces of the integrated circuit design;

comparing the design dimensions with the minimum electromigration dimensions; and

identifying violations of the fabrication process rules for the conductive signal traces of the integrated circuit when the design dimensions are less than the minimum electromigration dimensions.

2. A computer implemented method as claimed in claim 1, wherein the at least one current value indicates a peak current, and average current and an rms current of each top-level net.

3. A computer implemented method as claimed in claim 1, further comprising forming a top-level output error file that includes information concerning violations in each top-level net of the functional hierarchy of the integrated circuit design.