APAP I/O programmable router

• US 5,963,745 A
• Filed: 04/27/1995
• Issued: 10/05/1999
• Est. Priority Date: 11/13/1990
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Retter, Eric Eugene, Richardson, Robert Reist, Collins, Clive Allan, Rolfe, David Bruce, Dapp, Michael Charles, Kuchinski, David Christopher, Smoral, Vincent John, Knowles, Billy Jack, Nier, Richard Edward, Dieffenderfer, James Warren
• Primary Examiner(s): An, Meng-Ai T.
• Assistant Examiner(s): FOLLANSBEE, JOHN A
• Application Number:
  US08/430,114
• Time in Patent Office: 1,622 Days
• Field of Search: 395/800, 395/820, 395/800.1, 395/800.12, 395/800.13, 395/800.14, 395/200.68, 395/200.73, 395/200.79, 395/800.11, 364/DIG. 1, 364/DIG. 2
• US Class Current: 712/13
• CPC Class Codes: F02B 2075/027 four
• CPC Class Codes: G06F 15/17337 Direct connection machines, e.g. completely connected computers, point to point communication networks coupling between buses G06F13/4004
• CPC Class Codes: G06F 15/17343 wherein the interconnection is dynamically configurable, e.g. having loosely coupled nearest neighbor architecture reconfigurable processors arrays G06F15/7867
• CPC Class Codes: G06F 15/17368 non hierarchical topologies
• CPC Class Codes: G06F 15/17381 Two dimensional, e.g. mesh, torus
• CPC Class Codes: G06F 15/8007 single instruction multiple data [SIMD] multiprocessors
• CPC Class Codes: G06F 15/8015 One dimensional arrays, e.g. rings, linear arrays, buses
• CPC Class Codes: G06F 15/803 Three-dimensional arrays or hypercubes
• CPC Class Codes: G06F 7/483 Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers G06F7/4806, G06F7/4824, G06F7/49, G06F7/491, G06F7/544 take precedence
• CPC Class Codes: G06F 9/30 Arrangements for executing machine instructions, e.g. instruction decode for executing microinstructions G06F9/22
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/30167 of immediate specifier, e.g. constants
• CPC Class Codes: G06F 9/3017 Runtime instruction translation, e.g. macros
• CPC Class Codes: G06F 9/30181 Instruction operation extension or modification
• CPC Class Codes: G06F 9/30189 according to execution mode, e.g. mode flag
• CPC Class Codes: G06F 9/38 Concurrent instruction execution, e.g. pipeline or look ahead
• CPC Class Codes: G06F 9/3802 Instruction prefetching
• CPC Class Codes: G06F 9/3834 Maintaining memory consistency
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/3838 : Dependency mechanisms, e.g. register scoreboarding
• CPC Class Codes: G06F 9/3851 : from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3885 : using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/3887 : controlled by a single instruction for multiple data lanes [SIMD]
• CPC Class Codes: G06F 9/3889 : controlled by multiple instructions, e.g. MIMD, decoupled access or execute
• CPC Class Codes: G06F 9/3891 : organised in groups of units sharing resources, e.g. clusters

Abstract

A parallel array processor for massively parallel applications is formed with low power CMOS with DRAM processing while incorporating processing elements on a single chip. Eight processor memory elements on a single chip have their own associated processing element, significant memory, and I/O and are interconnected with a hypercube based, but modified, topology. These nodes are then interconnected, either by a hypercube, modified hypercube, or ring, or ring within ring network topology. The architecture uses all the pins for networking. Each chip has eight 16 bit processors, and eight respective 32K memories. I/O has three internal ports and one external port shared by the plural processors on the chip. Significant software flexibility is provided to enable quick implementation of existing programs written in common languages. The scalable chip has internal and external connections for broadcast and asynchronous SIMD, MIMD and SIMIMD (SIMD/MIMD) with dynamic switching of modes. A fully distributed programmable router is provided by the processing memory elements that form a node. There is program compatibility for the fully scalable system.

Claims

1. A parallel array computer system, comprising:

a plurality of nodes interconnected by a plurality of inter-node communication links in an inter-node array topology, each node having a plurality of processor memory elements, each processor memory element of each node including;

a processor and a local memory coupled to said processor;

an internal input and output port coupled to a parallel internal communication path directly connected to another processor memory element in the same node for bidirectional inter-processor communication therebetween;

an external input and output port coupled to a parallel external communication path directly connected to a processor memory element of another node for bidirectional inter-processor communication therebetween, wherein the parallel external communication path is one of said plurality of inter-node communication links; and

wherein the local memory includes stored instructions selectively executed by the processor for controlling routing data and control information with another processor memory element of the same node along said parallel internal communication path, and between the node containing the processing memory element and said another node along said parallel external communication path, independent of a centralized router providing routing for each of the processor memory elements within the same node, thereby providing for a router that is fully distributed among each of the processing memory elements of each of the nodes of the parallel array computer system; and

wherein said inter-node array links are exclusively provided by each parallel external communication path of said nodes, and said inter-node array topology is not dependent on said parallel internal communication path of each of said plurality of nodes.

2. A computer system according to claim 1 wherein each multi-processor memory element (PME) has 2n processors, wherein n is a nonzero positive integer, and said internal communication paths minimize delays due to chip crossings.

3. A computer system according to claim 1 wherein each multi-processor memory element (PME) has a processor, memory and fully distributed programmable routers within a single chip and said internal and said external communication paths minimize delays due to chip crossings, each processor memory element having means for fixed and floating point processing, routing and I/O control.

4. A computer system according to claim 1 further comprising within a processor memory element:

a native instruction set associated with said processor memory element for executing operations,

means for providing an expandable multiply function, and wherein said fully distributed programmable router selectively routes information in a one-dimensional left/right, two-dimensional NEWS matrix, three-dimensional NEWS/up-down, and a multidimensional hypercube,

and wherein said fully distributed programmable router includes a hardware distributed router provided by each processing memory element.

5. A computer system according to claim 1 organized as a massively parallel machine with the nodes interconnected as an dimensional network cluster with the parallel communication paths between processor memory elements along said internal and external communication paths providing a processing array, and wherein processing memory elements of an array have a transparent mode utilized when routing data between processing memory elements within a single chip for permitting reduction of the effective network diameter of a network of nodes.

6. A computer system according to claim 1 wherein one of said nodes has multiple processor memory elements, each processor memory element including 32K 16-bit words of said memory coupled with a 16-bit processor.

7. A computer system according to claim 6 wherein the number of processor memory elements in the node is eight and a plurality of the nodes are combined as groups of node clusters organized as a 2d modified hypercube.

8. A computer system according to claim 6 wherein the number of processor memory elements in the node is eight and a plurality of the nodes are combined as groups of node clusters organized as a 2d modified hypercube, with up to 64 clusters integrated in a network of node clusters to form a 4d modified hypercube of up to 32,768 processing memory elements.

9. A computer system according to claim 1 wherein a node processing memory element further comprises internal data flows including high speed hard registers to feed distributed ALU and I/O router registers and logic for all operations performed by said processing memory element.

10. A computer system according to claim 1 wherein the processing memory elements of a given node are contained on a chip and each of the processing memory elements includes an I/O port for off chip byte wide communication, and input ports that are connected such that data may be routed from input to the memory, or from an input address register to an output register via a direct parallel data path.

11. A computer system according to claim 1 wherein a node has multiple processor memory elements and is connected to other nodes in a cluster network with data routing by said fully distributed programmable router distributed between hardware and software, with software controlling most of the task sequencing function.

12. A computer system according to claim 1 wherein a node has multiple processor memory elements and is connected to other nodes in a cluster network with data routing distributed between hardware and software, with hardware provided for performing inner loop transfers of acquiring data from another processor memory element and minimizing overhead on the outer loops of the node.

13. A computer system according to claim 1 wherein a node has multiple processor memory elements and is connected to other nodes in a cluster network, each processor memory element having I/O programs at dedicated interrupt levels for managing the network.

14. A computer system according to claim 1 wherein a node has multiple processor memory elements and is connected to other nodes in a cluster network, each processor memory element having I/O programs at dedicated interrupt levels for managing the network, each processor memory element having interrupt registers and dedicating four interrupt levels to receiving data from four neighbors, a buffer provided at each interrupt level by loading registers at the interrupt level, and having IN and RETURN instruction pairs using a buffer address and transfer count to enable the processor memory element to accept words from an input bus and to store them to the buffer.