Method for integrating microelectromechanical devices with electronic circuitry

• US 5,963,788 A
• Filed: 11/19/1997
• Issued: 10/05/1999
• Est. Priority Date: 09/06/1995
• Status: Expired due to Term

• Current Assignee: Sandia Corporation (Martin Marietta Corporation)
• Original Assignee: Sandia Corporation (Martin Marietta Corporation)
• Inventors: Barron, Carole C., Fleming, James G., Montague, Stephen
• Primary Examiner(s): TRINH, MICHAEL MANH
• Application Number:
  US08/974,586
• Time in Patent Office: 685 Days
• Field of Search: 438/48, 438/50, 438/51, 438/52, 438/53, 438/199, 438/200, 438/691, 438/654, 438/644, 148/DIG. 105
• US Class Current: 438/48
• CPC Class Codes: B81C 1/00246 Monolithic integration, i.e. micromechanical structure and electronic processing unit are integrated on the same substrate
• CPC Class Codes: B81C 2203/0728 Pre-CMOS, i.e. forming the micromechanical structure before the CMOS circuit
• CPC Class Codes: G01P 2015/0828 the mass being of the paddle type being suspended at one of its longitudinal ends
• CPC Class Codes: G03F 7/094 Multilayer resist systems, e.g. planarising layers
• CPC Class Codes: G03F 9/70 for microlithography measuring printed patterns for monitoring overlay G03F7/70633 or focus G03F7/70641; projection system adjustment G03F7/70258; position control G03F7/70775
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/1305 Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: Y10S 148/105 Masks, metal

Abstract

A method is disclosed for integrating one or more microelectromechanical (MEM) devices with electronic circuitry on a common substrate. The MEM device can be fabricated within a substrate cavity and encapsulated with a sacrificial material. This allows the MEM device to be annealed and the substrate planarized prior to forming electronic circuitry on the substrate using a series of standard processing steps. After fabrication of the electronic circuitry, the electronic circuitry can be protected by a two-ply protection layer of titanium nitride (TiN) and tungsten (W) during an etch release process whereby the MEM device is released for operation by etching away a portion of a sacrificial material (e.g. silicon dioxide or a silicate glass) that encapsulates the MEM device. The etch release process is preferably performed using a mixture of hydrofluoric acid (HF) and hydrochloric acid (HCI) which reduces the time for releasing the MEM device compared to use of a buffered oxide etchant. After release of the MEM device, the TiN:W protection layer can be removed with a peroxide-based etchant without damaging the electronic circuitry.

Claims

1. A method for integrating a microelectromechanical (MEM) device with electronic circuitry on a substrate comprising steps for:

(a) etching a cavity within a first portion of the substrate;

(b) fabricating the MEM device within the cavity, and filling the cavity with a sacrificial material;

(c) fabricating the electronic circuitry comprising a plurality of transistors within a second portion of the substrate proximate to the first portion, and interconnecting the electronic circuitry to the MEM device;

(d) protecting the electronic circuitry by depositing a layer of tungsten to blanket the second portion of the substrate and cover the electronic circuitry; and

(e) releasing the MEM device for operation thereof by removing at least a portion of the sacrificial material filling the cavity by etching the sacrificial material with a first wet etchant which does not substantially remove the layer of tungsten protecting the electronic circuitry.

2. The method of claim 1 wherein the step for etching the cavity within the first portion of the substrate comprises etching the cavity into at least one semiconductor layer formed on the substrate.

3. The method of claim 1 wherein the substrate comprises silicon.

4. The method of claim 1 wherein the step for fabricating the MEM device within the cavity comprises steps for depositing and patterning by etching at least one layer of a micromachineable material selected from the group consisting of polysilicon, silicon dioxide, silicon nitride, silicate glass, metals and metal alloys.

5. The method of claim 4 wherein the step for filling the cavity with a sacrificial material comprises depositing a sacrificial material selected from the group consisting of silicon dioxide and a silicate glass within the cavity to fill the cavity.

6. The method of claim 1 wherein the step for fabricating the MEM device includes a step for annealing the MEM device, thereby relieving stress therein.

7. The method of claim 1 further including a step for planarizing the substrate prior to the step for fabricating the electronic circuitry.

8. The method of claim 1 wherein the step for fabricating the electronic circuitry comprises steps for fabricating a plurality of transistors selected from the group consisting of CMOS transistors, BiCMOS transistors, and bipolar transistors.

9. The method of claim 1 wherein the step for depositing the layer of tungsten comprises depositing the layer of tungsten by chemical vapor deposition.

10. The method of claim 1 wherein the layer of tungsten is deposited to a layer thickness of about 0.1-1 microns.

11. The method of claim 1 wherein the step for protecting the electronic circuitry further comprises a step for depositing an adhesion layer over the second portion of the substrate prior to the step for depositing the layer of tungsten.

12. The method of claim 11 wherein the adhesion layer comprises a layer of titanium nitride.

13. The method of claim 12 wherein the titanium nitride layer is deposited to a layer thickness of about 50 nanometers.

14. The method of claim 12 further including a step for removing the layers of tungsten and titanium nitride after the step for releasing the MEM device.

15. The method of claim 1 wherein the first wet etchant comprises hydrofluoric acid (HF).

16. The method of claim 15 wherein the first wet etchant further comprises hydrochloric acid (HCI).

17. The method of claim 1 further including a step for removing the layer of tungsten after the step for releasing the MEM device.

18. The method of claim 17 wherein the step for removing the layer of tungsten comprises exposing the layer of tungsten to a second wet etchant having a chemical composition different from the chemical composition of the first wet etchant.

19. The method of claim 18 wherein the second wet etchant comprises hydrogen peroxide.

20. A method for integrating a microelectromechanical (MEM) device with electronic circuitry on a substrate comprising steps for:

(a) fabricating the MEM device at least in part within or from a cavity formed in a first portion of the substrate and encapsulating the MEM device with a sacrificial material;

(b) fabricating the electronic circuitry in a second portion of the substrate, and interconnecting the electronic circuitry to the MEM device;

(c) depositing layers of titanium nitride and tungsten over the electronic circuitry for protecting the electronic circuitry from exposure to a first wet etchant comprising, at least in part, hydrofluoric acid; and

(d) releasing the MEM device for operation by etching away at least a portion of the sacrificial material encapsulating the MEM device with the first wet etchant.

21. The method of claim 20 wherein the substrate comprises silicon.

22. The method of claim 20 further including a step for annealing the encapsulated MEM device for relieving stress therein.

23. The method of claim 20 further including a step for planarizing the substrate prior to the step for fabricating the electronic circuitry.

24. The method of claim 20 wherein the step for fabricating the MEM device comprises steps for etching a cavity into the substrate, depositing a plurality of material layers into the cavity, and patterning by etching at least one of the material layers.

25. The method of claim 24 wherein the material layers comprise micromachineable materials selected from the group consisting of polysilicon, silicon dioxide, silicon nitride, silicate glass, metals and metal alloys.

26. The method of claim 20 wherein the step for fabricating the MEM device comprises steps for etching a cavity into a semiconductor layer formed above the substrate, depositing a plurality of material layers into the cavity, and patterning by etching at least one of the material layers.

27. The method of claim 26 wherein the material layers comprise micromachineable materials selected from the group consisting of polysilicon, silicon dioxide, silicon nitride, silicate glass, metals and metal alloys.

28. The method of claim 20 wherein the sacrificial material comprises silicon dioxide or a silicate glass.

29. The method of claim 20 wherein the step for fabricating the electronic circuitry comprises steps for fabricating a plurality of transistors selected from the group consisting of CMOS transistors, BiCMOS transistors, and bipolar transistors.

30. The method of claim 20 wherein the step for depositing layers of titanium nitride and tungsten over the electronic circuitry comprises depositing the layers of titanium nitride and tungsten by deposition processes selected from the group consisting of sputter deposition and chemical vapor deposition.

31. The method of claim 20 wherein the layer of titanium nitride is about 50 nanometers thick.

32. The method of claim 20 wherein the layer of tungsten is about 0.1-1 microns thick.

33. The method of claim 20 further including a step for removing the layers of titanium nitride and tungsten after the step for releasing the encapsulated MEM device.

34. The method of claim 33 wherein the step for removing the layers of titanium nitride and tungsten comprises exposing the layers of titanium nitride and tungsten to a second wet etchant having a chemical composition different from the chemical composition of the first wet etchant.

35. The method of claim 34 wherein the second wet etchant comprises, at least in part, hydrogen peroxide.

36. A method for integrating a microelectromechanical (MEM) device with electronic circuitry on a substrate comprising steps for:

(a) fabricating the MEM device at least in part within or from a cavity formed in a first portion of the substrate and encapsulating the MEM device with a sacrificial material;

(b) planarizing the substrate to remove any of the sacrificial material extending upward beyond the cavity thereby providing a substantially planar upper surface for the substrate;

(c) fabricating the electronic circuitry in a second portion of the substrate, and interconnecting the electronic circuitry to the MEM device;

(d) protecting the electronic circuitry by depositing layers of titanium nitride and tungsten over the electronic circuitry in the second portion of the substrate;

(e) releasing the MEM device by exposing the MEM device to a first wet etching comprising, at least in part, hydrofluoric acid for sufficient time to remove a portion of the sacrificial material encapsulating the MEM device; and

(f) removing the deposited layers of titanium nitride and tungsten protecting the electronic circuitry.

37. The method of claim 36 wherein the step for fabricating the MEM device comprises steps for etching a cavity into the substrate, depositing a plurality of material layers into the cavity, and patterning by etching at least one of the material layers.

38. The method of claim 37 wherein the substrate comprises silicon, and the material layers comprise micromachineable materials selected from the group consisting of polysilicon, silicon dioxide, silicon nitride, silicate glass, metals and metal alloys.

39. The method of claim 36 further including a step for annealing the MEM device for relieving stress therein.

40. The method of claim 36 wherein the electronic circuitry comprises a plurality of transistors.

41. The method of claim 40 wherein the transistors are selected from the group consisting of CMOS transistors, BiCMOS transistors, and bipolar transistors.

42. The method of claim 36 wherein the step for removing the deposited layers of titanium nitride and tungsten comprises exposing the layers of titanium nitride and tungsten to a second wet etchant having a chemical composition different from the chemical composition of the first wet etchant.

43. The method of claim 42 wherein the second wet etchant comprises, at least in part, hydrogen peroxide.