Silicon carbide MOSFET having self-aligned gate structure and method of fabrication

• US 5,963,791 A
• Filed: 07/25/1997
• Issued: 10/05/1999
• Est. Priority Date: 08/07/1992
• Status: Expired due to Fees

• Current Assignee: General Electric Company
• Original Assignee: General Electric Company
• Inventors: Edmond, John Adam, Palmour, John Williams, Brown, Dale Marius, Saia, Richard Joseph
• Primary Examiner(s): TRINH, MICHAEL MANH
• Application Number:
  US08/900,442
• Time in Patent Office: 802 Days
• Field of Search: 438/105, 438/931, 438/270, 438/271, 438/272, 438/269, 438/268, 438/589, 148/DIG. 148
• US Class Current: 438/105
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: Y10S 438/931 Silicon carbide semiconductor

Abstract

A SiC MOSFET having a self-aligned gate structure is fabricated upon a monocrystalline substrate layer, such as a p type conductivity α6H silicon carbide (SiC) substrate. An SiC n+ type conductivity layer is epitaxially grown on the substrate layer. A steep-walled groove is etched through the n+ SiC layer and partially into the p SiC layer at a location on the substrate where a MOSFET gate structure is desired. Subsequently, a thin layer of silicon dioxide and a layer of gate metal are successively deposited over the entire structure. The gate metal layer is deposited with sufficient thickness to substantially fill the groove. A layer of photoresist is applied to the entire surface of the gate metal layer. The photoresist and the underlying gate metal are then reactive ion etched down to the oxide layer, leaving gate metal remaining only in the groove. The gate metal and oxide layer form the self-aligned gate structure wherein the walls of the groove are automatically aligned with the edges of drain and source regions that are formed on either side of the groove.

Claims

1. A method of fabricating a metal oxide semiconductor device having a self-aligned gate structure comprising the steps of:

epitaxially depositing, upon a first silicon carbide layer of a first conductivity type, a uniformly deposited second silicon carbide layer of a second conductivity type, said first and second layers forming a monocrystalline silicon carbide structure;

patterning said uniformly deposited second layer to form a steep-walled groove therein;

applying a gate oxide layer over said second layer;

depositing a gate metal layer upon said gate oxide layer;

depositing a layer of photoresist material upon said gate metal layer;

etching said layer of photoresist material and said gate metal layer until said gate metal layer remains substantially only within said groove whereby said gate oxide layer and the remaining portion of said gate metal layer form a self-aligned gate structure; and

attaching electrodes to said gate metal layer and through said oxide layer to said second silicon carbide layer, wherein the attaching step further comprises the steps of;

depositing a dielectric layer upon said gate oxide layer and said remaining portion of said gate metal layer;

etching contact windows through said dielectric layer and said gate oxide layer to said second silicon carbide layer;

depositing a sintered contact metal within said windows;

opening a gate contact window through said dielectric layer to said remaining portion of said gate metal layer;

depositing in a selected pattern a metal layer to contact said sintered contact metal to form a source electrode and a drain electrode; and

depositing in a selected pattern a metal layer to contact said remaining portion of said gate metal layer to form a gate landing pad.

2. The method of claim 1 wherein said first silicon carbide layer comprises p type silicon carbide and said second silicon carbide layer comprises n type silicon carbide.

3. A method of fabricating a metal oxide semiconductor device having a self-aligned gate structure comprising the steps of:

epitaxially depositing, upon a first silicon carbide layer of a first conductivity type, a second silicon carbide layer of a second conductivity type, said first and second layers forming a monocrystalline silicon carbide structure;

patterning said second silicon carbide layer to form a steep-walled groove therein;

applying a thick oxide layer upon said second silicon carbide layer with sufficient depth to fill said groove;

patterning said thick oxide layer to form an opening therein in registry with said groove;

applying a gate oxide layer to the walls and bottom of said groove so as to line said walls and bottom of said groove therewith;

depositing a gate metal layer upon said gate oxide layer, said gate metal layer being wholly contained within said groove;

depositing a dielectric layer upon said gate metal layer and exposed portions of said gate oxide layer in said groove;

opening a first window in said dielectric layer to said gate metal layer;

opening second and third windows in said thick oxide layer to said second silicon carbide layer on either side of said groove; and

depositing a conductive material in each of said first, second and third windows to make contact with said gate metal layer so as to form a gate electrode, and to make contact with said second silicon carbide layer on either side of said groove so as to form a source electrode and a drain electrode respectively.

4. The method of claim 3 wherein the step of depositing a conductive material in each of said first, second, and third windows comprises the steps of:

depositing a sintered contact metal within said second and third windows;

depositing a metal layer to contact said sintered contact metal to form said source and drain electrodes; and

depositing a metal layer to contact said gate metal layer to form said gate electrode.

5. The method of claim 3 wherein said first silicon carbide layer comprises p type silicon carbide and said second silicon carbide layer comprises n type silicon carbide.

6. The method of claim 4 wherein said first silicon carbide layer comprises p type silicon carbide and said second silicon carbide layer comprises n type silicon carbide.