Single chip integrated circuit distributed shared memory (DSM) and communications nodes

• US 5,963,975 A
• Filed: 09/17/1997
• Issued: 10/05/1999
• Est. Priority Date: 04/19/1994
• Status: Expired due to Term

• Current Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Scepanovic, Ranko, Koford, James S., Boyle, Douglas B., Rostoker, Michael D., Jones, Edwin R.
• Primary Examiner(s): Swann, Tod R.
• Assistant Examiner(s): Chow, Christopher S.
• Application Number:
  US08/932,042
• Time in Patent Office: 748 Days
• Field of Search: 711/144, 711/145, 711/146, 711/117, 711/147, 711/148, 711/153, 364/134
• US Class Current: 711/147
• CPC Class Codes: G06F 12/0817 using directory methods

Abstract

The capacity of a cache memory is substantially reduced over that required for a multi-chip distributed shared memory (DSM) implementation to enable the cache memory, a main memory, a processor and requisite logic and control circuitry to fit on a single integrated circuit chip. The increased cache miss rate created by the reduced cache memory capacity is compensated for by the reduced cache miss resolution period resulting from integrating the main memory and processor on the single chip. The reduced cache miss resolution period enables the processor clock rate to be substantially increased, so that a processor having a simple functionality such as a reduced instruction set computer (RISC) processor can be utilized and still provide the required processing speed. The RISC processor is substantially smaller than a more complicated processor that would be required to provide the same processing speed in a multi-chip DSM implementation, thereby enabling the RISC processor to fit on the chip with the other elements. A single-chip communications node that can be used in telecommunications networks other than DSM includes a memory controller for providing local and remote memory coherency, and a bidirectional interconnect unit that converts memory access instructions into memory access messages and vice-versa.

Claims

1. A single integrated circuit chip distributed shared memory (DSM) node that is capable of operating at a predetermined processing speed, comprising:

a computing unit integral with said chip, comprising a processor, a cache controller, and a cache memory;

a main memory integral with said chip;

a bidirectional interconnect unit integral with said chip for connection to a remote node; and

a memory controller integral with said chip for interconnecting the processor, cache controller, cache memory, main memory and bidirectional interconnect unit and maintaining memory coherency between the cache memory, main memory and said remote node, wherein said memory controller includes a directory controller that stores and modifies a directory in the main memory;

in which

the cache memory has a capacity that is sufficiently small to enable the cache memory to fit on said chip but creates a substantial cache miss rate; and

the main memory has a cache miss resolution period that is sufficiently small to compensate for said cache miss rate and enable the node to operate at said predetermined processing speed.

2. A DSM node as in claim 1, in which the processor has a sufficiently simple functionality to enable the processor to fit on said chip and operate at a clock rate that is sufficiently high to enable the node to operate at said predetermined processing speed.

3. A DSM node as in claim 2, in which the processor has a Reduced Instruction Set Computer (RISC) functionality.

4. A DSM node as in claim 1, in which:

the memory controller generates outgoing memory access instructions for accessing memory locations in said remote node;

the interconnect unit converts said outgoing memory access instructions into outgoing memory access messages for transmission to said remote node; and

the interconnect unit further converts incoming memory access messages received from said remote node into incoming memory access instructions and applies said incoming memory access instructions to the memory controller.

5. A DSM node as in claim 4, further comprising an interconnect transceiver for asynchronously transmitting said outgoing memory access messages and receiving said incoming memory access messages.

6. A DSM node as in claim 5, in which the interconnect transceiver asynchronously transmits said outgoing memory access messages and receives said incoming memory access messages in the form of data packets.

7. A DSM node as in claim 1, in which the memory controller comprises a coherency controller for maintaining memory coherency between the cache memory, main memory and said remote node.

8. A DSM node as in claim 7, in which the coherency controller stores a directory in the main memory, the directory including a list of data stored in the cache memory, the main memory and said remote node.

9. A DSM node as in claim 1, further comprising an input-output (I/O) interface for connecting the processor to an input-output device.

10. A DSM node as in claim 1, in which:

the processor operates using virtual addresses;

the memory controller operates using physical addresses; and

the node further comprises a memory management unit for converting said virtual addresses into said physical addresses and vice-versa.

11. A single integrated circuit chip distributed shared memory (DSM) node, comprising:

a logic element integral with said chip;

a memory integral with said chip;

an interconnect unit integral with said chip for connection to a remote node; and

a memory controller integral with said chip for interconnecting the logic element, memory and interconnect unit, and for maintaining memory coherency between the memory and said remote node.

12. A single integrated circuit chip distributed shared memory (DSM) node, comprising:

a processor integral with said chip;

a cache memory integral with said chip;

a main memory integral with said chip;

a bidirectional interconnect unit integral with said chip for connection to a remote node; and

a memory controller integral with said chip for interconnecting the processor, cache memory, main memory and interconnect unit, and for maintaining memory coherency between the cache memory, main memory and said remote node.

13. A DSM node as in claim 12, in which the processor has a Reduced Instruction Set Computer (RISC) functionality.

14. A DSM node as in claim 12, in which:

the memory controller generates outgoing memory access instructions for accessing memory locations in said remote node;

the interconnect unit converts said outgoing memory access instructions into outgoing memory access messages for transmission to said remote node; and

the interconnect unit further converts incoming memory access messages received from said remote node into incoming memory access instructions and applies said incoming memory access instructions to the memory controller.

15. A DSM node as in claim 14, further comprising an interconnect transceiver for asynchronously transmitting said outgoing memory access messages and receiving said incoming memory access messages.

16. A DSM node as in claim 15, in which the interconnect transceiver asynchronously transmits said outgoing memory access messages and receives said incoming memory access messages in the form of data packets.

17. A DSM node as in claim 12, in which the memory controller comprises a coherency controller for maintaining memory coherency between the cache memory, main memory and said remote node.

18. A DSM node as in claim 17, in which the coherency controller stores a directory in the main memory, the directory including a list of data stored in the cache memory, main memory and said remote node.

19. A DSM node as in claim 12, further comprising an input-output (I/O) interface for connecting the processor to an input-output device.

20. A DSM node as in claim 12, in which:

the processor operates using virtual addresses;

the memory controller operates using physical addresses; and

the node further comprises a memory management unit for converting said virtual addresses into said physical addresses and vice-versa.

21. A single integrated circuit chip communications node for connecting a local memory to a remote node, comprising:

a computing unit integral with said chip, comprising a processor, a cache controller, and a cache memory;

a local memory integral with said chip;

a bidirectional interconnect unit integral with said chip for converting outgoing memory access instructions from said local memory into outgoing memory access messages for transmission to said remote node;

converting incoming memory access messages received from said remote node into incoming memory access instructions; and

applying said incoming memory access instructions to said local memory; and

a memory controller integral with said chip for maintaining memory coherency between said local memory and said remote node.

22. A communications node as in claim 21, in which the memory controller comprises a coherency controller for maintaining memory coherency between said local memory and said remote node.

23. A communications node as in claim 22, in which the coherency controller stores a directory in said local memory, said directory including a list of data stored in said local memory and said remote node.

24. A communications node as in claim 21, further comprising an interconnect transceiver for asynchronously transmitting said outgoing memory access messages and receiving said incoming memory access messages.

25. A communications node as in claim 24, in which the interconnect transceiver asynchronously transmits said outgoing memory access messages and receives said incoming memory access messages in the form of data packets.

26. A communications node as in claim 21, further comprising an input-output (I/O) interface for connecting the memory controller to an input-output device.