Method of determining the printability of photomask defects

• US 5,965,306 A
• Filed: 10/15/1997
• Issued: 10/12/1999
• Est. Priority Date: 10/15/1997
• Status: Expired due to Term

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Ferguson, Richard Alan, Wong, Alfred Kwok-Kit, Mansfield, Scott Marshall
• Primary Examiner(s): ROSASCO, STEPHEN D
• Application Number:
  US08/950,620
• Time in Patent Office: 727 Days
• Field of Search: 430/5, 430/22, 430/322, 356/390, 356/394
• US Class Current: 430/22
• CPC Class Codes: G03F 1/84 Inspecting
• CPC Class Codes: G03F 7/70616 Monitoring the printed patterns
• CPC Class Codes: G03F 7/70625 Dimensions, e.g. line width, critical dimension [CD], profile, sidewall angle or edge roughness
• CPC Class Codes: G03F 7/7065 Defects, e.g. optical inspection of patterned layer for defects

Abstract

A method for determining if an undesirable feature on a photomask will adversely affect the performance of the semiconductor integrated circuit device that the mask is being used to create. The method includes inspecting the photomask for undesirable features and analyzing the designed features close to the defects. This analysis is performed on lithographic images that represent the image that is transferred onto the semiconductor wafer by the lithography process. This analysis takes into account the effect of variations that are present in the lithography process. Through knowledge of the effects of variations in mask critical dimension of a feature on the lithographic image of that feature, the analysis results in the assignment of an equivalent critical dimension error to the defect. This equivalent critical dimension error is then compared to the mask critical dimension error specification to determine whether or not the defect will adversely affect the device.

Claims

1. A method for determining if defects on a photomask will adversely affect the performance of a semiconductor device on a wafer, said device being created by said photomask through a lithographic process, said method comprising the steps of:

a) inspecting said photomask to find said defects;

b) analyzing process conditions that cause designed features close to said defects to be printed on said wafer with dimensions which fall within the wafer critical dimension tolerance that is applicable to said designed features;

c) assigning an equivalent critical dimension error to said defects; and

d) comparing said equivalent critical dimension error to a mask critical dimension error tolerance for determining whether said defects will adversely affect the performance of said semiconductor device.

2. The method as recited in claim 1, wherein when said equivalent critical dimension error is less than said mask critical dimension error tolerance, said defect will not adversely affect the performance of said semiconductor device, and when said equivalent critical dimension error is larger than said mask critical dimension error tolerance, said defect will potentially affect the performance of said semiconductor device and will be required to be repaired.

3. The method as recited in claim 1, wherein said analysis is performed by using measurements taken on lithographic images that represent the image that is transferred onto said wafer by said lithographic process.

4. The method as recited in claim 3, wherein said analysis of said process conditions further comprises examining an amount of tolerable variation existing in said lithographic process while generating features on said wafer that are contained within a wafer critical dimension tolerance, said variation comprising focus and dose variations.

5. The method as recited in claim 4, wherein said wafer critical dimension tolerance derives a relationship between variations in the size of a feature on said photomask and said amount of tolerable variation of said lithographic process, said variations in the size of the feature being referred to as mask critical dimension errors.

6. The method as recited in claim 5, wherein said relationship further derives said mask critical dimension tolerance for all critical features within said photomask.

7. The method as recited in claim 5, wherein said size is a one-dimensional cross-sectional size.

8. The method as recited in claim 5, wherein said size is a two-dimensional area.

9. The method as recited in claim 5, wherein said wafer critical dimension tolerance is derived by analyzing product specifications that comprise performance, size and cost.

10. The method as recited in claim 5, wherein said relationship assigns said equivalent critical dimension error.

11. The method as recited in claim 5, further comprising analyzing process conditions that are required for generating lithographic features, said analysis comprising all process steps preceding said lithographic process.

12. The method as recited in claim 5, wherein said relationship is determined by simulating said lithographic process.

13. The method as recited in claim 12, wherein the effect of process steps following said lithographic process is included in said simulation.

14. The method as recited in claim 5, wherein said relationship is determined by printing features of various dimensions on said wafer with said lithographic process, and then measuring said features on said wafer, said lithographic process including a plurality of focus and dose conditions such that effects of process variations can be analyzed.

15. The method as recited in claim 5, wherein said relationship is determined by measuring features of various dimensions with an imaging system that emulates a lithographic exposure tool, said measurements including a plurality of focus and dose conditions such that effects of process variations can be analyzed.

16. The method as recited in claim 15, wherein the effect of process steps following said lithographic process are applied to said images.

17. The method as recited in claim 5, wherein structures are included when designing said photomask, said structures spanning a range of said mask critical dimension tolerance.

18. The method as recited in claim 17, wherein said structures are included in a section of said design that does not influence the functionality of said semiconductor device.

19. The method as recited in claim 17, wherein said structures are measured using an aerial image measurement system.

20. The method as recited in claim 17, wherein said structures are printed on said wafer by said lithographic process and are then further measured on said wafer.

21. The method as recited in claim 5, wherein films present on said wafer and settings of an exposure tool for said lithographic process are analyzed, said analysis resulting in a metric that defines the quality of said lithographic process and a value for said metric to achieve for said lithographic process to meet product specifications.

22. The method as recited in claim 21, wherein said product specifications include performance, size and cost.

23. The method as recited in claim 21, wherein said metric further quantifies said relationship between mask critical dimension error and said tolerable variation of said lithographic process, resulting in a first functional dependence of said metric on said mask critical dimension error.

24. The method as recited in claim 23, further comprising inverting said first functional dependence resulting in a second functional dependence of said mask critical dimension error on said metric.

25. The method as recited in claim 24, wherein said mask critical dimension tolerance is further determined by finding said mask critical dimension error at said value for said metric required to meet said product specifications.

26. The method as recited in claim 3, wherein said lithographic images are obtained by transferring a mask pattern from said photomask onto said wafer.

27. The method as recited in claim 3, wherein said lithographic images are aerial images, said aerial images being generated by an imaging system that emulates a lithographic exposure tool, said imaging system being referred to as an aerial image measurement system (AIMS).

28. The method as recited in claim 27, wherein said AIMS generates said aerial images by emulating optical components of said lithographic exposure tool.

29. The method as recited in claim 27, wherein said AIMS generates said aerial images by simulating photomask patterns based on measurements taken of said photomask patterns.

30. The method as recited in claim 27, wherein said AIMS is part of an inspection system.

31. The method as recited in claim 27, wherein design data for said photomask is provided to said AIMS.

32. The method as recited in claim 31, wherein said design data derives a relationship between variations in the size of a feature on said photomask and an amount of tolerable variation in said lithographic process.

33. The method as recited in claim 1, wherein said analysis further comprises analyzing the effect of process steps that follow said lithographic process, said process steps comprising photoresist development and etch.

34. A method for determining if a resolution enhancement feature that is desirable on a photomask will adversely affect the performance of a semiconductor device on a wafer, said device created by said photomask through a lithographic process, said resolution enhancement feature being included on said photomask to improve the ability of another critical feature on said photomask to be printed on said wafer, said method comprising the steps of:

a) locating said resolution enhancement feature on said photomask;

b) analyzing process conditions that result in said critical feature close to said resolution enhancement feature to be printed on said wafer with dimensions which fall within the wafer critical dimension tolerance that is applicable to said critical feature;

c) assigning an equivalent critical dimension error to said resolution enhancement feature; and

d) comparing said equivalent critical dimension error to a mask critical dimension error tolerance for determining whether said resolution enhancement feature adversely affects said semiconductor device.

35. The method as recited in claim 34, wherein said resolution enhancement feature alters a radiation transmission of said photomask, said resolution enhancement feature being characterized as an optical proximity correction (OPC) feature.

36. The method as recited in claim 35, wherein said OPC feature is a serif.

37. The method as recited in claim 35, wherein said OPC feature is a hammerhead.

38. The method as recited in claim 35, wherein said OPC feature is a scattering bar.

39. The method as recited in claim 35, wherein said OPC feature is an anti-scattering bar.

40. The method as recited in claim 35, wherein said OPC feature is added to the design of said semiconductor device by a computer program that adds OPC features to semiconductor designs to improve the ability of said lithographic process to transfer said design onto said wafer, said semiconductor design being modified by said computer program and said modified design being considered an OPC corrected design.

41. The method as recited in claim 35, wherein said semiconductor design is available at an inspection tool.

42. The method as recited in claim 35, wherein said OPC corrected design is available at an inspection tool.

43. The method as recited in claim 34, wherein said resolution enhancement feature alters the phase of radiation passing through said photomask, said resolution enhancement feature being considered a phase shifting feature.

44. The method as recited in claim 43, wherein said phase shifting feature is made by removing material from a substrate of said photomask.

45. The method as recited in claim 43, wherein said phase shifting feature is made by depositing a material on a substrate of said photomask, said material transmitting a portion of said radiation.

46. The method as recited in claim 45, wherein said portion of said radiation is approximately 100%.

47. The method as recited in claim 45, wherein said portion of said radiation is approximately 5-10%.

48. A method for determining if a feature that is desirable on a photomask will adversely affect the performance of a semiconductor device on a wafer, said device created by said photomask through a lithographic process, said method comprising the steps of:

a) locating said desirable feature on said photomask;

b) analyzing process conditions that result in said desirable feature to be printed on said wafer with dimensions that fall within the wafer critical dimension tolerance that is applicable to said feature;

c) assigning an equivalent critical dimension error to said feature, wherein said equivalent critical dimension error compares the variation of said desirable feature to a critical dimension variation of another reference feature; and

d) comparing said equivalent critical dimension error to a mask critical dimension error tolerance for determining whether said desirable feature adversely affects said semiconductor device.

49. The method as recited in claim 48, wherein locating said desirable feature is performed on an inspection tool capable of measuring dimensions of critical features.

50. The method as recited in claim 48, wherein locating said desirable feature is performed by finding coordinates of said desirable feature from design data of said photomask.

51. The method as recited in claim 48, wherein said equivalent critical dimension error is determined by analyzing an image of said photomask, said image being approximately equivalent to an image of said photomask that would be printed in photoresist using said lithographic process, and said mask critical dimension error tolerance being determined by analysis of said reference feature that differs from said desirable feature.

52. The method as recited in claim 51, wherein said reference feature has a nearest neighboring feature that is placed at a distance away from said reference feature that is different from the distance between said desirable feature and its nearest neighboring feature.