Semiconductor device including field effect transistor

• US 5,965,918 A
• Filed: 03/18/1999
• Issued: 10/12/1999
• Est. Priority Date: 03/19/1998
• Status: Expired due to Term

• Current Assignee: Toshiba Memory Corporation (Kioxia Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Ono, Mizuki
• Primary Examiner(s): Ngo, Ngan V.
• Application Number:
  US09/271,168
• Time in Patent Office: 208 Days
• Field of Search: 257/347, 257/349, 257/410, 257/638, 257/645, 257/651
• US Class Current: 257/347
• CPC Class Codes: H01L 21/76264 SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
• CPC Class Codes: H01L 21/76283 Lateral isolation by refilling of trenches with dielectric material
• CPC Class Codes: H01L 21/764 Air gaps H01L21/76264 takes precedence
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/78603 characterised by the insulating substrate or support H01L29/78657 takes precedence

Abstract

An insulating film having a low dielectric constant lower than that of silicon oxide is arranged between a silicon support layer and a silicon active layer. A channel region, source/drain regions, and a device isolation region are formed in the active layer. A gate electrode is arranged on the channel region through a gate insulating film. The active layer is covered with a TEOS film in which contact holes are formed. The contact holes are filled with wiring layers connected to the source/drain regions and the gate electrode.

Claims

1. A semiconductor device including a field effect transistor, comprising:

a support layer consisting essentially of silicon;

a buried insulating layer arranged on said support layer;

an active layer consisting essentially of silicon and arranged on said buried insulating layer, said buried insulating layer being interposed between said support layer and said active layer;

source/drain regions and a channel region interposed therebetween, which are formed in said active layer to be in contact with said buried insulating layer;

a gate electrode facing said channel region through an insulating film; and

source/drain electrodes connected to said source/drain regions, respectively,

wherein said buried insulating layer comprises a low-dielectric-constant region having a dielectric constant of from 1 to 3.9, along a route of lines of electric force extending from said channel region to each of said source/drain regions through said buried insulating layer to form a capacitive coupling between said channel region and each of said source/drain regions.

2. The device according to claim 1, wherein said low-dielectric-constant region consists essentially of silicon oxide doped with fluorine at a concentration set to be more than zero and not more than 12 atm %.

3. The device according to claim 1, wherein said low-dielectric-constant region consists essentially of silicon oxide doped with carbon at a concentration set to be more than zero and not more than 2.9 times larger than a density of Si atoms in said low-dielectric-constant region.

4. The device according to claim 1, wherein said low-dielectric-constant region is formed of a gap region which is a vacuum or filled with an inactive gas.

5. The device according to claim 1, wherein said low-dielectric-constant region has a thickness between said support layer and said active layer, larger than a length of said channel region, between said source/drain regions.

6. The device according to claim 1, wherein said buried insulating layer further comprises a high-dielectric-constant region having a dielectric constant higher than that of said low-dielectric-constant region, and interposed between said support layer and said channel region.

7. The device according to claim 6, wherein said high-dielectric-constant region consists essentially of silicon oxide.

8. A semiconductor device including a field effect transistor, comprising:

a support layer consisting essentially of silicon;

a buried insulating layer arranged on said support layer and comprising a low-dielectric-constant region having a dielectric constant of from 1 to 3.9;

an active layer consisting essentially of silicon and arranged on said buried insulating layer, said buried insulating layer being interposed between said support layer and said active layer;

source/drain regions and a channel region interposed therebetween, which are formed in said active layer to be in contact with said buried insulating layer, said source/drain regions facing said low-dielectric-constant region;

a gate electrode facing said channel region through an insulating film; and

source/drain electrodes connected to said source/drain regions, respectively.

9. The device according to claim 8, wherein said channel region and each of said source/drain regions form a interface therebetween above said low-dielectric-constant region.

10. The device according to claim 9, wherein said low-dielectric-constant region is in contact with said support layer.

11. The device according to claim 10, wherein said channel region and said source/drain regions are in contact with said low-dielectric-constant region.

12. The device according to claim 11, wherein said low-dielectric-constant region occupies substantially all of said buried insulating layer.

13. The device according to claim 11, wherein said buried insulating layer further comprises a high-dielectric-constant region having a dielectric constant higher than that of said low-dielectric-constant region, and interposed between said support layer and said channel region.

14. The device according to claim 13, wherein said high-dielectric-constant region consists essentially of silicon oxide.

15. The device according to claim 8, wherein said low-dielectric-constant region has a thickness between said support layer and said active layer, larger than a length of said channel region, between said source/drain regions.

16. The device according to claim 8, wherein said gate electrode and said source/drain electrodes are arranged on a side of said active layer opposite to said buried insulating layer.

17. The device according to claim 8, wherein said low-dielectric-constant region consists essentially of silicon oxide doped with fluorine at a concentration set to be more than zero and not more than 12 atm %.

18. The device according to claim 8, wherein said low-dielectric-constant region consists essentially of silicon oxide doped with carbon at a concentration set to be more than zero and not more than 2.9 times larger than a density of Si atoms in said low-dielectric-constant region.

19. The device according to claim 8, wherein said low-dielectric-constant region is formed of a gap region which is a vacuum or filled with an inactive gas.